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Message-ID: <176771739996.2222090.14758454921102802504.robh@kernel.org>
Date: Tue, 6 Jan 2026 10:36:40 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: David Lechner <dlechner@...libre.com>
Cc: Sean Anderson <sean.anderson@...ux.dev>, linux-iio@...r.kernel.org,
	Nuno Sá <nuno.sa@...log.com>,
	devicetree@...r.kernel.org,
	Michael Hennerich <michael.hennerich@...log.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Jonathan Cameron <jic23@...nel.org>, linux-kernel@...r.kernel.org,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Mark Brown <broonie@...nel.org>, Andy Shevchenko <andy@...nel.org>,
	linux-spi@...r.kernel.org,
	Marcelo Schmitt <marcelo.schmitt@...log.com>
Subject: Re: [PATCH v4 6/9] spi: dt-bindings: adi,axi-spi-engine: add
 multi-lane support


On Fri, 19 Dec 2025 15:32:14 -0600, David Lechner wrote:
> Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
> controller has a capability to read multiple data words at the same
> time (e.g. for use with simultaneous sampling ADCs). The current FPGA
> implementation can support up to 8 data lanes at a time (depending on a
> compile-time configuration option).
> 
> Signed-off-by: David Lechner <dlechner@...libre.com>
> ---
> v4 changes:
> - Update to use spi-{tx,rx}-bus-width properties.
> ---
>  .../devicetree/bindings/spi/adi,axi-spi-engine.yaml       | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>


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