linux-kernel - Re: [PATCH 1/1] arm64: dts: rockchip: Enable PCIe for ArmSoM Sige1

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Message-ID: <1c5005b7-ceb9-4915-ad58-a9aa86cce394@kwiboo.se>
Date: Tue, 6 Jan 2026 11:21:06 +0100
From: Jonas Karlman <jonas@...boo.se>
To: Chukun Pan <amadeus@....edu.cn>, Heiko Stuebner <heiko@...ech.de>
Cc: Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 1/1] arm64: dts: rockchip: Enable PCIe for ArmSoM Sige1

Hi Chukun,

On 1/6/2026 11:00 AM, Chukun Pan wrote:
> Enable the RTL8125 network controller and corresponding PHY
> connected via PCIe on the ArmSoM Sige1.
> 
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>

This matches what I currently have in my pending to do final test and
then sent out branch at [1], so this is:

Reviewed-by: Jonas Karlman <jonas@...boo.se>

For the remaining RK3528 boards we should split up the pciemX_pins
pinctrl group similar to how it has been done for RK3588, as there are
freeze issues in U-Boot or problem using strict GPIO usage in Linux if
we do not property configure the reset-gpios pin to GPIO func.

[1] https://github.com/Kwiboo/linux-rockchip/commits/next-20251219-rk3528/

Regards,
Jonas

> ---
>  .../boot/dts/rockchip/rk3528-armsom-sige1.dts  | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts
> index 6e21579365a5..c41af8fc0c8d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts
> @@ -232,6 +232,10 @@ sdio_pwrseq: sdio-pwrseq {
>  	};
>  };
>  
> +&combphy {
> +	status = "okay";
> +};
> +
>  &cpu0 {
>  	cpu-supply = <&vdd_arm>;
>  };
> @@ -293,6 +297,14 @@ rgmii_phy: ethernet-phy@1 {
>  	};
>  };
>  
> +&pcie {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie20_perstn>;
> +	reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
> +	vpcie3v3-supply = <&vcc_3v3>;
> +	status = "okay";
> +};
> +
>  &pinctrl {
>  	bluetooth {
>  		bt_reg_on_h: bt-reg-on-h {
> @@ -324,6 +336,12 @@ r_led: r-led {
>  		};
>  	};
>  
> +	pcie {
> +		pcie20_perstn: pcie20-perstn {
> +			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +	};
> +
>  	rtc {
>  		rtc_int_l: rtc-int-l {
>  			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;