linux-kernel - Re: [PATCH v3 2/3] arm64: dts: freescale: Add support for Variscite DART-MX95

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Message-ID: <aVzjQEhpv4fenAWF@shlinux89>
Date: Tue, 6 Jan 2026 18:26:08 +0800
From: Peng Fan <peng.fan@....nxp.com>
To: Stefano Radaelli <stefano.radaelli21@...il.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	Stefano Radaelli <stefano.r@...iscite.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Alexander Stein <alexander.stein@...tq-group.com>,
	Dario Binacchi <dario.binacchi@...rulasolutions.com>,
	Markus Niebel <Markus.Niebel@...group.com>,
	Primoz Fiser <primoz.fiser@...ik.com>,
	Yannic Moog <y.moog@...tec.de>, Josua Mayer <josua@...id-run.com>,
	Francesco Dolcini <francesco.dolcini@...adex.com>,
	imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 2/3] arm64: dts: freescale: Add support for Variscite
 DART-MX95

On Mon, Jan 05, 2026 at 11:24:02AM +0100, Stefano Radaelli wrote:
>From: Stefano Radaelli <stefano.r@...iscite.com>
>
>Add device tree support for the Variscite DART-MX95 system on module.
>This SOM is designed to be used with various carrier boards.
>
>The module includes:
>- NXP i.MX95 MPU processor
>- Up to 16GB of LPDDR5 memory
>- Up to 128GB of eMMC storage memory
>- Integrated 10/100/1000 Mbps Ethernet Transceiver
>- Codec audio WM8904
>- WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
>
>Only SOM-specific peripherals are enabled by default. Carrier board
>specific interfaces are left disabled to be enabled in the respective
>carrier board device trees.
>
>Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/
>Signed-off-by: Stefano Radaelli <stefano.r@...iscite.com>
>---
>v3:
>- Fix specific node name with generic one
>- Audio regulator cleanup
>
> .../boot/dts/freescale/imx95-var-dart.dtsi    | 461 ++++++++++++++++++
> 1 file changed, 461 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi
>
>diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi
>new file mode 100644
>index 000000000000..ac9691aa73f3
>--- /dev/null
>+++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi
>@@ -0,0 +1,461 @@
>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>+/*
>+ * Common dtsi for Variscite DART-MX95
>+ *
>+ * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/
>+ *
>+ * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
>+ *
>+ */
>+
>+/dts-v1/;
>+
>+#include <dt-bindings/leds/common.h>
>+#include <dt-bindings/usb/pd.h>
>+#include "imx95.dtsi"
>+
>+/ {
>+	model = "Variscite DART-MX95 Module";
>+	compatible = "variscite,var-dart-mx95", "fsl,imx95";
>+
>+	memory@...00000 {
>+		device_type = "memory";
>+		reg = <0x0 0x80000000 0 0x80000000>;
>+	};
>+
>+	reg_1p8v: regulator-1p8v {
>+		compatible = "regulator-fixed";
>+		regulator-max-microvolt = <1800000>;
>+		regulator-min-microvolt = <1800000>;
>+		regulator-name = "+V1.8_SW";
>+	};
>+
>+	reg_3p3v: regulator-3p3v {
>+		compatible = "regulator-fixed";
>+		regulator-max-microvolt = <3300000>;
>+		regulator-min-microvolt = <3300000>;
>+		regulator-name = "+V3.3_SW";
>+	};
>+
>+	reg_audio: regulator-audio-vdd {
>+		compatible = "regulator-fixed";
>+		regulator-name = "wm8904_supply";
>+		regulator-min-microvolt = <3300000>;
>+		regulator-max-microvolt = <3300000>;
>+	};
>+
>+	reg_vref_1v8: regulator-adc-vref {
>+		compatible = "regulator-fixed";
>+		regulator-name = "vref_1v8";
>+		regulator-min-microvolt = <1800000>;
>+		regulator-max-microvolt = <1800000>;
>+	};
>+
>+	reserved-memory {
>+		ranges;
>+		#address-cells = <2>;
>+		#size-cells = <2>;
>+
>+		linux_cma: linux,cma {
>+			compatible = "shared-dma-pool";
>+			alloc-ranges = <0 0x80000000 0 0x7F000000>;
>+			reusable;
>+			size = <0 0x3c000000>;
>+			linux,cma-default;
>+		};
>+
>+		vdev0vring0: vdev0vring0@...00000 {
>+			reg = <0 0x88000000 0 0x8000>;
>+			no-map;
>+		};
>+
>+		vdev0vring1: vdev0vring1@...08000 {
>+			reg = <0 0x88008000 0 0x8000>;
>+			no-map;
>+		};
>+
>+		vdev1vring0: vdev1vring0@...10000 {
>+			reg = <0 0x88010000 0 0x8000>;
>+			no-map;
>+		};
>+
>+		vdev1vring1: vdev1vring1@...18000 {
>+			reg = <0 0x88018000 0 0x8000>;
>+			no-map;
>+		};
>+
>+		vdevbuffer: vdevbuffer@...20000 {
>+			compatible = "shared-dma-pool";
>+			reg = <0 0x88020000 0 0x100000>;
>+			no-map;
>+		};
>+
>+		rsc_table: rsc-table@...20000 {
>+			reg = <0 0x88220000 0 0x1000>;
>+			no-map;
>+		};
>+
>+		vpu_boot: vpu_boot@...00000 {
>+			reg = <0 0xa0000000 0 0x100000>;
>+			no-map;
>+		};

CM7 support still not landed, and VPU support also not ready in upstream.
You may need to drop these reserved nodes.

>+	};
>+
...
>+};
>+
>+&adc1 {
>+	vref-supply = <&reg_vref_1v8>;
>+	status = "okay";
>+};
>+
>+&enetc_port0 {
>+	pinctrl-names = "default";
>+	pinctrl-0 = <&pinctrl_enetc0>;
>+	phy-handle = <&ethphy0>;
>+	/*
>+	 * The required RGMII TX and RX 2ns delays are implemented directly
>+	 * in hardware via passive delay elements on the SOM PCB.
>+	 * No delay configuration is needed in software via PHY driver.
>+	 */
>+	phy-mode = "rgmii";
>+	status = "okay";
>+};
>+
>+&lpi2c8 {
>+	clock-frequency = <400000>;
>+	pinctrl-names = "default","gpio","sleep";
>+	pinctrl-0 = <&pinctrl_lpi2c8>;
>+	pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
>+	pinctrl-2 = <&pinctrl_lpi2c8_gpio>;
>+	scl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
>+	sda-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;

Per my understanding, GPIO_OPEN_DRAIN is better to be included.

>+
>+&scmi_iomuxc {
>+	pinctrl_bt: btgrp {
>+		fsl,pins = <
>+			IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28				0x31e
>+		>;
>+	};
>+
>+	pinctrl_emdio: emdiogrp{
>+		fsl,pins = <
>+			IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC			0x57e
>+			IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO			0x97e
>+		>;
>+	};
>+
>+	pinctrl_phy0res: phy0resgrp{
>+		fsl,pins = <
>+			IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16				0x31e
>+		>;
>+	};
>+
>+	pinctrl_enetc0: enetc0grp {
>+		fsl,pins = <
>+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3			0x57e
>+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2			0x57e
>+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1			0x57e
>+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0			0x57e
>+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL		0x57e
>+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK		0x58e
>+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL		0x57e
>+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK		0x58e
>+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0			0x57e
>+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1			0x57e
>+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2			0x57e
>+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3			0x57e
>+		>;
>+	};
>+
>+	pinctrl_lpi2c8: lpi2c8grp {
>+		fsl,pins = <
>+			IMX95_PAD_GPIO_IO10__LPI2C8_SDA					0x40000b9e
>+			IMX95_PAD_GPIO_IO11__LPI2C8_SCL					0x40000b9e
>+		>;
>+	};
>+
>+	pinctrl_lpi2c8_gpio: lpi2c8gpiogrp {
>+		fsl,pins = <
>+			IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10				0x31e
>+			IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11				0x31e
>+		>;
>+	};
>+
>+	pinctrl_sai3: sai3grp {
>+		fsl,pins = <
>+			IMX95_PAD_GPIO_IO17__SAI3_MCLK					0x31e
>+			IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK				0x31e
>+			IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC				0x31e
>+			IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0				0x31e
>+			IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0				0x31e
>+		>;
>+	};
>+
>+	pinctrl_uart5: uart5grp {
>+		fsl,pins = <
>+			IMX95_PAD_GPIO_IO00__LPUART5_TX					0x31e
>+			IMX95_PAD_GPIO_IO01__LPUART5_RX					0x31e
>+			IMX95_PAD_GPIO_IO02__LPUART5_CTS_B				0x31e
>+			IMX95_PAD_GPIO_IO03__LPUART5_RTS_B				0x31e
>+		>;
>+	};
>+
>+	pinctrl_usdhc1: usdhc1grp {
>+		fsl,pins = <
>+			IMX95_PAD_SD1_CLK__USDHC1_CLK					0x158e
>+			IMX95_PAD_SD1_CMD__USDHC1_CMD					0x138e
>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0				0x138e
>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1				0x138e
>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2				0x138e
>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3				0x138e
>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4				0x138e
>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5				0x138e
>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6				0x138e
>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7				0x138e
>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE				0x158e
>+		>;
>+	};
>+
>+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>+		fsl,pins = <
>+			IMX95_PAD_SD1_CLK__USDHC1_CLK					0x158e
>+			IMX95_PAD_SD1_CMD__USDHC1_CMD					0x138e
>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0				0x138e
>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1				0x138e
>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2				0x138e
>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3				0x138e
>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4				0x138e
>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5				0x138e
>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6				0x138e
>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7				0x138e
>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE				0x158e
>+		>;
>+	};
>+
>+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>+		fsl,pins = <
>+			IMX95_PAD_SD1_CLK__USDHC1_CLK					0x15fe
>+			IMX95_PAD_SD1_CMD__USDHC1_CMD					0x13fe
>+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0				0x13fe
>+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1				0x13fe
>+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2				0x13fe
>+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3				0x13fe
>+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4				0x13fe
>+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5				0x13fe
>+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6				0x13fe
>+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7				0x13fe
>+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE				0x15fe
>+		>;
>+	};
>+
>+	pinctrl_usdhc3_gpio: usdhc3gpiogrp {
>+		fsl,pins = <
>+			IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27				0x31e
>+			IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29				0x31e
>+		>;
>+	};
>+
>+	pinctrl_usdhc3: usdhc3grp {
>+		fsl,pins = <
>+			IMX95_PAD_SD3_CLK__USDHC3_CLK					0x158e
>+			IMX95_PAD_SD3_CMD__USDHC3_CMD					0x138e
>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0				0x138e
>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1				0x138e
>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2				0x138e
>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3				0x138e
>+		>;
>+	};
>+
>+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>+		fsl,pins = <
>+			IMX95_PAD_SD3_CLK__USDHC3_CLK					0x158e
>+			IMX95_PAD_SD3_CMD__USDHC3_CMD					0x138e
>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0				0x138e
>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1				0x138e
>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2				0x138e
>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3				0x138e
>+		>;
>+	};
>+
>+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>+		fsl,pins = <
>+			IMX95_PAD_SD3_CLK__USDHC3_CLK					0x15fe
>+			IMX95_PAD_SD3_CMD__USDHC3_CMD					0x13fe
>+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0				0x13fe
>+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1				0x13fe
>+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2				0x13fe
>+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3				0x13fe
>+		>;
>+	};
>+};

Better keep scmi_iomuxc at end of the file.

Regards
Peng