linux-kernel - Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support

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Message-ID: <875x9fuj7i.fsf@gmail.com>
Date: Tue, 06 Jan 2026 12:58:40 +0300
From: Mikhail Rudenko <mike.rudenko@...il.com>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I
 <kishon@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
 <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Joel Stanley
 <joel@....id.au>, Andrew  Jeffery <andrew@...econstruct.com.au>, Bjorn
 Helgaas <bhelgaas@...gle.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kwilczynski@...nel.org>, Manivannan
  Sadhasivam
 <mani@...nel.org>, Linus Walleij <linus.walleij@...aro.org>, Philipp Zabel
 <p.zabel@...gutronix.de>, Neil Armstrong <neil.armstrong@...aro.org>,
 linux-aspeed@...ts.ozlabs.org, linux-pci@...r.kernel.org,
 linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Andrew
 Jeffery <andrew@...id.au>, openbmc@...ts.ozlabs.org,
 linux-gpio@...r.kernel.org, Mikhail Rudenko <mike.rudenko@...il.com>
Subject: Re: [PATCH v7 0/7] Add ASPEED PCIe Root Complex support

Hi Jacky,

On 2025-12-16 at 09:49 +08, Jacky Chou <jacky_chou@...eedtech.com> wrote:

> This patch series adds support for the ASPEED PCIe Root Complex,
> including device tree bindings, pinctrl support, and the PCIe host controller
> driver. The patches introduce the necessary device tree nodes, pinmux groups,
> and driver implementation to enable PCIe functionality on ASPEED platforms.
> Currently, the ASPEED PCIe Root Complex only supports a single port.
>
> Summary of changes:
> - Add device tree binding documents for ASPEED PCIe PHY and PCIe RC
> - Update MAINTAINERS for new bindings and driver
> - Implement ASPEED PCIe PHY driver
> - Implement ASPEED PCIe Root Complex host controller driver
>
> This series has been tested on AST2600/AST2700 platforms and enables PCIe device
> enumeration and operation.

First of all, thank you for your efforts in getting this driver
upstreamed! I am trying to understand whether this driver supports
PCIe devices that have an I/O port BAR, where CPU access to I/O ports
is required for proper device operation.

If I understand correctly, this line in the Aspeed 2600 dtsi file
declares the I/O port range:

    ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000

During system initialization, the pci_remap_iospace() function in
arch/arm/mm/ioremap.c maps the physical address range
0x00018000-0x00020000 to the virtual address PCI_IO_VIRT_BASE
(0xfee00000). After this mapping, inb() and outb() calls work by
converting I/O port addresses to virtual addresses starting at
PCI_IO_VIRT_BASE, then performing reads and writes to those virtual
addresses.

What I don't understand is this: according to the Aspeed 2600
datasheet, the address range 0x00000000-0x0fffffff (which contains
0x00018000-0x00020000) is mapped to Firmware SPI Memory. This would
mean that outb() operations get routed to memory-mapped SPI flash
instead of PCIe.

It seems like there's a missing piece to this puzzle. Could you help
clarify how this is supposed to work?

--
Kind regards,
Mikhail Rudenko