linux-kernel - Re: [PATCH 5/7] perf/x86/intel: Add core PMU support for Novalake

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Message-ID: <18cc180b-7ce0-46d1-a6f6-af9368f3cc40@intel.com>
Date: Thu, 8 Jan 2026 11:35:36 -0800
From: "Chen, Zide" <zide.chen@...el.com>
To: Dapeng Mi <dapeng1.mi@...ux.intel.com>,
 Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
 Arnaldo Carvalho de Melo <acme@...nel.org>,
 Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
 Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Dapeng Mi <dapeng1.mi@...el.com>, Falcon Thomas <thomas.falcon@...el.com>,
 Xudong Hao <xudong.hao@...el.com>
Subject: Re: [PATCH 5/7] perf/x86/intel: Add core PMU support for Novalake



On 11/19/2025 9:34 PM, Dapeng Mi wrote:
> This patch enables core PMU support for Novalake, covering both P-core
> and E-core. It includes Arctic Wolf-specific counters, PEBS constraints,
> and the OMR registers table.
> 
> Since Coyote Cove shares the same PMU capabilities as Panther Cove, the
> existing Panther Cove PMU enabling functions are reused for Coyote Cove.
> 
> For detailed information about counter constraints, please refer to
> section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation.
> 
> ISE: https://www.intel.com/content/www/us/en/content-details/869288/intel-architecture-instruction-set-extensions-programming-reference.html
> 
> Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
> ---
>  arch/x86/events/intel/core.c | 99 ++++++++++++++++++++++++++++++++++++
>  arch/x86/events/intel/ds.c   | 11 ++++
>  arch/x86/events/perf_event.h |  2 +
>  3 files changed, 112 insertions(+)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 9f2a93fe23df..a3a1e6e670f8 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -232,6 +232,29 @@ static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
>  	EVENT_CONSTRAINT_END
>  };
>  
> +static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
> +	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> +	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
> +	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
> +	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
> +	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
> +	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
> +	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
> +	INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
> +	INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
> +	INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
> +	INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),

Should be these?

INTEL_UEVENT_CONSTRAINT(0x03b7, 0x4),
INTEL_UEVENT_CONSTRAINT(0x04b7, 0x8),