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Message-ID: <b455ea34-dc59-454e-a1d5-cb8db3a586fb@linux.intel.com>
Date: Fri, 9 Jan 2026 09:31:04 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: "Chen, Zide" <zide.chen@...el.com>, Peter Zijlstra
<peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
Dapeng Mi <dapeng1.mi@...el.com>, Falcon Thomas <thomas.falcon@...el.com>,
Xudong Hao <xudong.hao@...el.com>
Subject: Re: [PATCH 1/7] perf/x86/intel: Support newly introduced 4 OMR MSRs
for DMR & NVL
On 1/9/2026 3:34 AM, Chen, Zide wrote:
>
> On 11/19/2025 9:34 PM, Dapeng Mi wrote:
>> Diamond Rapids and Nova Lake feature an expanded facility called
>> the Off-Module Response (OMR) facility, which replaces the Off-Core
>> Response (OCR) Performance Monitoring of previous processors.
>>
>> Legacy microarchitectures used the OCR facility to evaluate off-core
>> and multi-core off-module transactions. The properly renamed, OMR
>> facility, improves the OCR capability for scalable coverage of new
>> memory systems of multi-core module systems.
>>
>> Similarly with OCR, 4 additional off-module configuration MSRs
>> OFFMODULE_RSP_0 ~ OFFMODULE_RSP_3 are introduced to specify
>> attributes of the off-module transaction.
>>
>> For more details about OMR, please refer to section 16.1 "OFF-MODULE
>> RESPONSE (OMR) FACILITY" in ISE documentation.
>>
>> This patch adds support for these 4 OMR events.
>>
>> ISE link: https://www.intel.com/content/www/us/en/content-details/869288/intel-architecture-instruction-set-extensions-programming-reference.html
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
>> ---
>> arch/x86/events/intel/core.c | 45 +++++++++++++++++++++++---------
>> arch/x86/events/perf_event.h | 5 ++++
>> arch/x86/include/asm/msr-index.h | 5 ++++
>> 3 files changed, 42 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index aad89c9d9514..5970f7c20101 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -3529,17 +3529,24 @@ static int intel_alt_er(struct cpu_hw_events *cpuc,
>> struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
>> int alt_idx = idx;
>>
>> - if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
>> - return idx;
>> -
>> - if (idx == EXTRA_REG_RSP_0)
>> - alt_idx = EXTRA_REG_RSP_1;
>> -
>> - if (idx == EXTRA_REG_RSP_1)
>> - alt_idx = EXTRA_REG_RSP_0;
>> + if (idx == EXTRA_REG_RSP_0 || idx == EXTRA_REG_RSP_1) {
>> + if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
>> + return idx;
>> + if (++alt_idx > EXTRA_REG_RSP_1)
>> + alt_idx = EXTRA_REG_RSP_0;
>> + if (config & ~extra_regs[alt_idx].valid_mask)
>> + return idx;
>> + }
>>
>> - if (config & ~extra_regs[alt_idx].valid_mask)
>> - return idx;
>> + if (idx >= EXTRA_REG_OMR_0 && idx <= EXTRA_REG_OMR_3) {
>> + if (!(x86_pmu.flags & PMU_FL_HAS_OMR))
>> + return idx;
>> + if (++alt_idx > EXTRA_REG_OMR_3)
>> + alt_idx = EXTRA_REG_OMR_0;
>> + if (config &
>> + ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask)
> Why minus EXTRA_REG_OMR_0?
This is to get the valid_mask of correct pre-defined extra_regs entry. ALL
the entries of extra_regs for OCR/OMR must be put the head of the whole
extra_regs entries (from index 0 starts), so we need to minus the
EXTRA_REG_OMR_0 base.
See below comments of intel_pnc_extra_regs[].
static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
/* must define OMR_X first, see intel_alt_er() */
INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
EVENT_EXTRA_END
};
I suppose I need to add a comment here to avoid the confusion. Thanks.
>
>> + return idx;
>> + }
>>
>> return alt_idx;
>> }
>> @@ -3547,16 +3554,28 @@ static int intel_alt_er(struct cpu_hw_events *cpuc,
>> static void intel_fixup_er(struct perf_event *event, int idx)
>> {
>> struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
>> - event->hw.extra_reg.idx = idx;
>> + int omr_idx;
>>
>> - if (idx == EXTRA_REG_RSP_0) {
>> + event->hw.extra_reg.idx = idx;
>> + switch (idx) {
>> + case EXTRA_REG_RSP_0:
>> event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
>> event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
>> event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
>> - } else if (idx == EXTRA_REG_RSP_1) {
>> + break;
>> + case EXTRA_REG_RSP_1:
>> event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
>> event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
>> event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
> Keep same style?
> case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
Yeah, good idea. Thanks.
>
>> + break;
>> + case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
>> + omr_idx = idx - EXTRA_REG_OMR_0;
>> + event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK;
>> + event->hw.config |= 1ULL << (8 + omr_idx);
>> + event->hw.extra_reg.reg = MSR_OMR_0 + omr_idx;
>> + break;
>> + default:
>> + pr_warn("The extra reg idx %d is not supported.\n", idx);
>> }
>> }
>>
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