linux-kernel - Re: [PATCH v4 1/2] PCI: endpoint: Add BAR subrange mapping support

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Message-ID: <aV9638ebwqc4bsbd@ryzen>
Date: Thu, 8 Jan 2026 10:37:35 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Koichiro Den <den@...inux.co.jp>
Cc: jingoohan1@...il.com, mani@...nel.org, lpieralisi@...nel.org,
	kwilczynski@...nel.org, robh@...nel.org, bhelgaas@...gle.com,
	Frank.Li@....com, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/2] PCI: endpoint: Add BAR subrange mapping support

On Thu, Jan 08, 2026 at 01:41:47PM +0900, Koichiro Den wrote:
> Extend the PCI endpoint core to support mapping subranges within a BAR.
> Introduce a new 'submap' field and a 'use_submap' flag in struct
> pci_epf_bar so an endpoint function driver can request inbound mappings
> that fully cover the BAR.
> 
> The submap array describes the complete BAR layout (no overlaps and no
> gaps are allowed to avoid exposing untranslated address ranges). This
> provides the generic infrastructure needed to map multiple logical
> regions into a single BAR at different offsets, without assuming a
> controller-specific inbound address translation mechanism. Also, the
> array must be sorted in ascending order by offset.
> 
> No controller-specific implementation is added in this commit.
> 
> Signed-off-by: Koichiro Den <den@...inux.co.jp>

What I don't really like is that you don't have any checks at all in:
pci_epc_set_bar() if the controller actually supports the submap feature.

AFAICT, for non-DWC drivers, e.g.:
drivers/pci/controller/cadence/pcie-cadence-ep.c
drivers/pci/controller/pcie-rcar-ep.c
drivers/pci/controller/pcie-rockchip-ep.c

They have no idea about submapping, so they will silently ignore
pci_epf_bar.use_submap.

I think that we should somehow expose that an EndPoint Controller(EPC)
supports the submap feature.

That way pci_epc_set_bar() can return an error for an EPC that does not
support it.

Perhaps something like:

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1195d401df19..b8eb069f6d57 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -622,15 +622,26 @@ static int dw_pcie_ep_start(struct pci_epc *epc)
 	return dw_pcie_start_link(pci);
 }
 
+static struct pci_epc_features dw_pcie_ep_features;
+
 static const struct pci_epc_features*
 dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
 {
 	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+	const struct pci_epc_features *glue_epc_features;
 
 	if (!ep->ops->get_features)
 		return NULL;
 
-	return ep->ops->get_features(ep);
+	glue_epc_features = ep->ops->get_features(ep);
+
+	memcpy(&dw_pcie_ep_features, glue_epc_features,
+	       sizeof(dw_pcie_ep_features));
+
+	/* All DWC based glue drivers support inbound subrange mapping */
+	dw_pcie_ep_features.subrange_mapping = true;
+
+	return &dw_pcie_ep_features;
 }
 
 static const struct pci_epc_ops epc_ops = {
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index ca7f19cc973a..8804daaf8376 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -596,6 +596,9 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 	if (!epc_features)
 		return -EINVAL;
 
+	if (epf_bar->flags && !epc_features->subrange_mapping)
+		return -EINVAL;
+
 	if (epc_features->bar[bar].type == BAR_RESIZABLE &&
 	    (epf_bar->size < SZ_1M || (u64)epf_bar->size > (SZ_128G * 1024)))
 		return -EINVAL;
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 4286bfdbfdfa..898a29e7d6f7 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -223,6 +223,8 @@ struct pci_epc_bar_desc {
 /**
  * struct pci_epc_features - features supported by a EPC device per function
  * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
+ * @subrange_mapping: indicate if the EPC device can map inbound subranges for a
+ *                    BAR
  * @msi_capable: indicate if the endpoint function has MSI capability
  * @msix_capable: indicate if the endpoint function has MSI-X capability
  * @intx_capable: indicate if the endpoint can raise INTx interrupts
@@ -231,6 +233,7 @@ struct pci_epc_bar_desc {
  */
 struct pci_epc_features {
 	unsigned int	linkup_notifier : 1;
+	unsigned int	subrange_mapping : 1;
 	unsigned int	msi_capable : 1;
 	unsigned int	msix_capable : 1;
 	unsigned int	intx_capable : 1;



The memcpy in dw_pcie_ep_get_features() is a bit ugly.
I guess the alternative is to change all the DWC based glue drivers
to return a "struct pci_epc_features*" instead of a "const struct pci_epc_features*"
such that dw_pcie_ep_get_features() can simply set subrange_mapping = true in the
struct pci_epc_features returned by the glue driver.


Kind regards,
Niklas