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Message-ID: <e5d1d9ce-0268-4b1b-9ce9-2b871926acbf@kernel.org>
Date: Mon, 12 Jan 2026 08:32:58 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Aleksander Jan Bajkowski <olek2@...pl>
Cc: benjamin.larsson@...exis.eu, chester.a.unal@...nc9.com,
 davem@...emloft.net, angelogioacchino.delregno@...labora.com,
 ansuelsmth@...il.com, conor+dt@...nel.org, herbert@...dor.apana.org.au,
 krzk+dt@...nel.org, matthias.bgg@...il.com, robh@...nel.org,
 sergio.paracuellos@...il.com, tsbogend@...ha.franken.de,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-mediatek@...ts.infradead.org, linux-mips@...r.kernel.org
Subject: Re: [PATCH v3 1/3] dt-bindings: crypto: eip93: add clock gate and
 reset line

On 11/01/2026 14:36, Aleksander Jan Bajkowski wrote:
> Hi Krzysztof,
> 
> On 1/3/26 15:11, Krzysztof Kozlowski wrote:
>> On Fri, Jan 02, 2026 at 04:47:33PM +0100, Aleksander Jan Bajkowski wrote:
>>> Add the clock gate and reset line, both of which are available
>>> on the Airoha AN7581.
>>>
>>> Signed-off-by: Aleksander Jan Bajkowski <olek2@...pl>
>>> ---
>>> v3:
>>> - introduce patch
>>> ---
>>>   .../crypto/inside-secure,safexcel-eip93.yaml       | 14 ++++++++++++++
>>>   1 file changed, 14 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
>>> index 997bf9717f9e..c6c99c08dc68 100644
>>> --- a/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
>>> +++ b/Documentation/devicetree/bindings/crypto/inside-secure,safexcel-eip93.yaml
>>> @@ -48,20 +48,34 @@ properties:
>>>     interrupts:
>>>       maxItems: 1
>>>   
>>> +  clocks:
>>> +    maxItems: 1
>>> +
>>> +  resets:
>>> +    maxItems: 1
>>> +
>>>   required:
>>>     - compatible
>>>     - reg
>>>     - interrupts
>>> +  - clocks
>>> +  - resets
>> That's ABI break without explanation in the commit msg.
>>
> I think that the reset line and clock gate are available on all SoCs
> with this IP Core. Should the reset line and clock gate only be

Not related. I did not say that hardware has or has not. I speak about
ABI, so the interface.

> required for newly added SoCs, and remain optional for existing ones?

Best regards,
Krzysztof

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