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<AM7P189MB10095424D5EECEF98761C227E381A@AM7P189MB1009.EURP189.PROD.OUTLOOK.COM>
Date: Mon, 12 Jan 2026 08:42:54 +0100
From: Maud Spierings <maud_spierings@...mail.com>
To: guodong@...cstar.com
Cc: ajones@...tanamicro.com, alex@...ti.fr, anup@...infault.org,
aou@...s.berkeley.edu, conor+dt@...nel.org, conor@...nel.org,
cyy@...self.name, daniel.lezcano@...aro.org, devicetree@...r.kernel.org,
dlan@...too.org, gregkh@...uxfoundation.org, jirislaby@...nel.org,
krzk+dt@...nel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org,
lkundrak@...sk, palmer@...belt.com, paul.walmsley@...ive.com,
pjw@...nel.org, robh@...nel.org, samuel.holland@...ive.com,
spacemit@...ts.linux.dev, tglx@...utronix.de, xypron.glpk@....de,
zhangmeng.kevin@...ux.spacemit.com
Subject: Re: [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of
SpacemiT K3 SoC
> + mimsic: interrupt-controller@...00000 {
> + compatible = "spacemit,k3-imsics", "riscv,imsics";
> + reg = <0x0 0xf1000000 0x0 0x10000>;
> + #interrupt-cells = <0>;
> + #msi-cells = <0>;
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
> + <&cpu2_intc 11>, <&cpu3_intc 11>,
> + <&cpu4_intc 11>, <&cpu5_intc 11>,
> + <&cpu6_intc 11>, <&cpu7_intc 11>;
> + msi-controller;
> + riscv,guest-index-bits = <6>;
> + riscv,hart-index-bits = <4>;
> + riscv,num-guest-ids = <511>;
> + riscv,num-ids = <511>;
> +
> + status = "disabled";
> + };
> +
> + maplic: interrupt-controller@...00000 {
> + compatible = "spacemit,k3-aplic", "riscv,aplic";
> + reg = <0x0 0xf1800000 0x0 0x4000>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + msi-parent = <&mimsic>;
> + riscv,children = <&saplic>;
> + riscv,delegate = <&saplic 1 512>;
> + riscv,num-sources = <512>;
> +
> + status = "disabled";
> + };
from reading the chatter on v3 I think the right status here may be
"reserved", for elements that are reserved by firmware. But I could be
mistaken.
Kind regards,
Maud
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