linux-kernel - Re: [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAH1PCMatYTfE58-O7ftt4dmr3tvssnD4UrSGEJSbHkFYgT_afQ@mail.gmail.com>
Date: Mon, 12 Jan 2026 15:59:02 +0800
From: Guodong Xu <guodong@...cstar.com>
To: Maud Spierings <maud_spierings@...mail.com>
Cc: ajones@...tanamicro.com, alex@...ti.fr, anup@...infault.org, 
	aou@...s.berkeley.edu, conor+dt@...nel.org, conor@...nel.org, 
	cyy@...self.name, daniel.lezcano@...aro.org, devicetree@...r.kernel.org, 
	dlan@...too.org, gregkh@...uxfoundation.org, jirislaby@...nel.org, 
	krzk+dt@...nel.org, linux-kernel@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org, lkundrak@...sk, 
	palmer@...belt.com, paul.walmsley@...ive.com, pjw@...nel.org, robh@...nel.org, 
	samuel.holland@...ive.com, spacemit@...ts.linux.dev, tglx@...utronix.de, 
	xypron.glpk@....de, zhangmeng.kevin@...ux.spacemit.com
Subject: Re: [PATCH v4 10/11] riscv: dts: spacemit: add initial device tree of
 SpacemiT K3 SoC

On Mon, Jan 12, 2026 at 3:43 PM Maud Spierings
<maud_spierings@...mail.com> wrote:
>
> > +             mimsic: interrupt-controller@...00000 {
> > +                     compatible = "spacemit,k3-imsics", "riscv,imsics";
> > +                     reg = <0x0 0xf1000000 0x0 0x10000>;
> > +                     #interrupt-cells = <0>;
> > +                     #msi-cells = <0>;
> > +                     interrupt-controller;
> > +                     interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
> > +                                           <&cpu2_intc 11>, <&cpu3_intc 11>,
> > +                                           <&cpu4_intc 11>, <&cpu5_intc 11>,
> > +                                           <&cpu6_intc 11>, <&cpu7_intc 11>;
> > +                     msi-controller;
> > +                     riscv,guest-index-bits = <6>;
> > +                     riscv,hart-index-bits = <4>;
> > +                     riscv,num-guest-ids = <511>;
> > +                     riscv,num-ids = <511>;
> > +
> > +                     status = "disabled";
> > +             };
> > +
> > +             maplic: interrupt-controller@...00000 {
> > +                     compatible = "spacemit,k3-aplic", "riscv,aplic";
> > +                     reg = <0x0 0xf1800000 0x0 0x4000>;
> > +                     #interrupt-cells = <2>;
> > +                     interrupt-controller;
> > +                     msi-parent = <&mimsic>;
> > +                     riscv,children = <&saplic>;
> > +                     riscv,delegate = <&saplic 1 512>;
> > +                     riscv,num-sources = <512>;
> > +
> > +                     status = "disabled";
> > +             };
>
>
> from reading the chatter on v3 I think the right status here may be
> "reserved", for elements that are reserved by firmware. But I could be
> mistaken.

Thanks Maud. Good catch. I think you are right, both M-mode maplic and mimsic
should be listed as "reserved" to signify that they are intended to be used
in OpenSBI, not the S-mode kernel.

I will fix that in the next version.

BR,
Guodong Xu

>
> Kind regards,
> Maud