[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <db601a8f-6486-48df-928e-b398f8d4fcc0@amd.com>
Date: Mon, 12 Jan 2026 10:39:08 +0100
From: Michal Simek <michal.simek@....com>
To: linux-kernel@...r.kernel.org, monstr@...str.eu, git@....com
Cc: Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
"moderated list:ARM/ZYNQ ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] arm64: zynqmp: Fix DTOVL warning about graphs in kv/kr260
On 1/8/26 09:24, Michal Simek wrote:
> DTC is generating warnings about missing port like:
> DTOVL arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
> arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
> /fragment@..._overlay__: graph port node name should be 'port'
> ...
>
> That's why change description and add it directly to dpsub mode to contain
> full description with also port.
>
> Signed-off-by: Michal Simek <michal.simek@....com>
> ---
>
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 10 ++++++----
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 10 ++++++----
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 12 +++++++-----
> arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 12 +++++++-----
> 4 files changed, 26 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
> index b82a056be2f9..507be24e71c0 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
> @@ -147,11 +147,13 @@ &zynqmp_dpsub {
> phy-names = "dp-phy0";
> phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
> assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>
> -&out_dp {
> - dpsub_dp_out: endpoint {
> - remote-endpoint = <&dpcon_in>;
> + ports {
> + out_dp: port@5 {
> + dpsub_dp_out: endpoint {
> + remote-endpoint = <&dpcon_in>;
> + };
> + };
> };
> };
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
> index 4dcf92a2158f..68394f02e8fb 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
> @@ -148,11 +148,13 @@ &zynqmp_dpsub {
> phy-names = "dp-phy0";
> phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
> assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>
> -&out_dp {
> - dpsub_dp_out: endpoint {
> - remote-endpoint = <&dpcon_in>;
> + ports {
> + out_dp: port@5 {
> + dpsub_dp_out: endpoint {
> + remote-endpoint = <&dpcon_in>;
> + };
> + };
> };
> };
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> index 923a70d750bf..e7417af8ae01 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
> @@ -3,7 +3,7 @@
> * dts file for KV260 revA Carrier Card
> *
> * (C) Copyright 2020 - 2022, Xilinx, Inc.
> - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
> *
> * SD level shifter:
> * "A" - A01 board un-modified (NXP)
> @@ -125,11 +125,13 @@ &zynqmp_dpsub {
> phy-names = "dp-phy0", "dp-phy1";
> phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
> assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>
> -&out_dp {
> - dpsub_dp_out: endpoint {
> - remote-endpoint = <&dpcon_in>;
> + ports {
> + out_dp: port@5 {
> + dpsub_dp_out: endpoint {
> + remote-endpoint = <&dpcon_in>;
> + };
> + };
> };
> };
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> index 563e750b0e08..7a05180e58b4 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
> @@ -3,7 +3,7 @@
> * dts file for KV260 revA Carrier Card
> *
> * (C) Copyright 2020 - 2022, Xilinx, Inc.
> - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
> + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
> *
> * Michal Simek <michal.simek@....com>
> */
> @@ -110,11 +110,13 @@ &zynqmp_dpsub {
> phy-names = "dp-phy0", "dp-phy1";
> phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
> assigned-clock-rates = <27000000>, <25000000>, <300000000>;
> -};
>
> -&out_dp {
> - dpsub_dp_out: endpoint {
> - remote-endpoint = <&dpcon_in>;
> + ports {
> + out_dp: port@5 {
> + dpsub_dp_out: endpoint {
> + remote-endpoint = <&dpcon_in>;
> + };
> + };
> };
> };
>
This should be updated because it generates another warning that's why v2 is
required.
M
Powered by blists - more mailing lists