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Message-ID: <20260114182055.46029-24-terry.bowman@amd.com>
Date: Wed, 14 Jan 2026 12:20:44 -0600
From: Terry Bowman <terry.bowman@....com>
To: <dave@...olabs.net>, <jonathan.cameron@...wei.com>,
<dave.jiang@...el.com>, <alison.schofield@...el.com>,
<dan.j.williams@...el.com>, <bhelgaas@...gle.com>, <shiju.jose@...wei.com>,
<ming.li@...omail.com>, <Smita.KoralahalliChannabasappa@....com>,
<rrichter@....com>, <dan.carpenter@...aro.org>,
<PradeepVineshReddy.Kodamati@....com>, <lukas@...ner.de>,
<Benjamin.Cheatham@....com>, <sathyanarayanan.kuppuswamy@...ux.intel.com>,
<linux-cxl@...r.kernel.org>, <vishal.l.verma@...el.com>, <alucerop@....com>,
<ira.weiny@...el.com>
CC: <linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<terry.bowman@....com>
Subject: [PATCH v14 23/34] cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers
In preparation for CXL VH (Virtual Host) topology protocol error handling,
add RAS capability registered mapping for all ports in a CXL VH topology.
This includes the RAS capabilities of Switch Upstream Ports, Switch
Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports
("downstream")
Update cxl_port_add_dport() to map the upstream RAS capability on first
'dport' attach, and downstream RAS capability on each 'dport' attach.
Arrange for dport mappings to be released at del_dport() time.
Signed-off-by: Terry Bowman <terry.bowman@....com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>
Reviewed-by: Dave Jiang <dave.jiang@...el.com>
[djbw: reword changelog, fix devm handling]
Co-developed-by: Dan Williams <dan.j.williams@...el.com>
Signed-off-by: Dan Williams <dan.j.williams@...el.com>
---
Changes in v13->v14:
- Correct message spelling (Terry)
---
drivers/cxl/core/port.c | 2 +-
drivers/cxl/core/ras.c | 11 +++++++++++
drivers/cxl/cxl.h | 2 ++
drivers/cxl/cxlpci.h | 4 ++++
drivers/cxl/port.c | 37 +++++++++++++++++++++++++++++++++++
tools/testing/cxl/Kbuild | 1 +
tools/testing/cxl/test/mock.c | 12 ++++++++++++
7 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 2184c20af011..2c4e28e7975c 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1451,7 +1451,7 @@ static void del_dport(struct cxl_dport *dport)
{
struct cxl_port *port = dport->port;
- devm_release_action(&port->dev, unlink_dport, dport);
+ devres_release_group(&port->dev, dport);
}
static void del_dports(struct cxl_port *port)
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 84abcf90fa99..76ac567724e3 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -162,6 +162,17 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport)
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_ras_setup, "CXL");
+void devm_cxl_port_ras_setup(struct cxl_port *port)
+{
+ struct cxl_register_map *map = &port->reg_map;
+
+ map->host = &port->dev;
+ if (cxl_map_component_regs(map, &port->regs,
+ BIT(CXL_CM_CAP_CAP_ID_RAS)))
+ dev_dbg(&port->dev, "Failed to map RAS capability\n");
+}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL");
+
void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)
{
void __iomem *addr;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 46491046f101..805923693707 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -607,6 +607,7 @@ struct cxl_dax_region {
* @parent_dport: dport that points to this port in the parent
* @decoder_ida: allocator for decoder ids
* @reg_map: component and ras register mapping parameters
+ * @regs: mapped component registers
* @nr_dports: number of entries in @dports
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
* @commit_end: cursor to track highest committed decoder for commit ordering
@@ -628,6 +629,7 @@ struct cxl_port {
struct cxl_dport *parent_dport;
struct ida decoder_ida;
struct cxl_register_map reg_map;
+ struct cxl_component_regs regs;
int nr_dports;
int hdm_end;
int commit_end;
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index e41bb93d583a..ef4496b4e55e 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -82,6 +82,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev);
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state);
void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
+void devm_cxl_port_ras_setup(struct cxl_port *port);
#else
static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
@@ -93,6 +94,9 @@ static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport)
{
}
+static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
+{
+}
#endif
#endif /* __CXL_PCI_H__ */
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 8f8fc98c1428..0d6e010e21ca 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -176,11 +176,29 @@ static struct cxl_port *cxl_port_devres_group(struct cxl_port *port)
DEFINE_FREE(cxl_port_group_free, struct cxl_port *,
if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T))
+static struct cxl_dport *cxl_dport_devres_group(struct cxl_dport *dport)
+{
+ if (!devres_open_group(&dport->port->dev, dport, GFP_KERNEL))
+ return ERR_PTR(-ENOMEM);
+ return dport;
+}
+DEFINE_FREE(cxl_dport_group_free, struct cxl_dport *,
+ if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->port->dev, _T))
+
static void cxl_port_group_close(struct cxl_port *port)
{
devres_remove_group(&port->dev, port);
}
+/*
+ * Unlike the port group, that just facilitates unwind of setup failures, the
+ * dport group needs to stay live for del_dport() to reference.
+ */
+static void cxl_dport_group_close(struct cxl_dport *dport)
+{
+ devres_close_group(&dport->port->dev, dport);
+}
+
static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
struct device *dport_dev)
{
@@ -209,6 +227,13 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
rc = devm_cxl_switch_port_decoders_setup(port);
if (rc)
return ERR_PTR(rc);
+
+ /*
+ * RAS setup is optional, either driver operation can continue
+ * on failure, or the device does not implement RAS registers.
+ */
+ devm_cxl_port_ras_setup(port);
+
/*
* Note, when nr_dports returns to zero the port is unregistered
* and triggers cleanup. I.e. no need for open-coded release
@@ -220,12 +245,24 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
if (IS_ERR(new_dport))
return new_dport;
+ /*
+ * Establish a group for all dport resources that need to be released
+ * when the dport is deleted.
+ */
+ struct cxl_dport *dport_group __free(cxl_dport_group_free) =
+ cxl_dport_devres_group(new_dport);
+ if (IS_ERR(dport_group))
+ return ERR_CAST(dport_group);
+
rc = cxl_dport_autoremove(new_dport);
if (rc)
return ERR_PTR(rc);
+ devm_cxl_dport_ras_setup(new_dport);
+
cxl_switch_parse_cdat(new_dport);
+ cxl_dport_group_close(no_free_ptr(dport_group));
cxl_port_group_close(no_free_ptr(port_group));
dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n",
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
index 7250bedf0448..6c516019600e 100644
--- a/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@ -13,6 +13,7 @@ ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
ldflags-y += --wrap=hmat_get_extended_linear_cache_size
ldflags-y += --wrap=cxl_add_dport_by_dev
ldflags-y += --wrap=devm_cxl_switch_port_decoders_setup
+ldflags-y += --wrap=devm_cxl_port_ras_setup
DRIVERS := ../../../drivers
CXL_SRC := $(DRIVERS)/cxl
diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
index 8883357ee50d..a0b87bbb2f75 100644
--- a/tools/testing/cxl/test/mock.c
+++ b/tools/testing/cxl/test/mock.c
@@ -246,6 +246,18 @@ void __wrap_devm_cxl_dport_ras_setup(struct cxl_dport *dport)
}
EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_dport_ras_setup, "CXL");
+void __wrap_devm_cxl_port_ras_setup(struct cxl_port *port)
+{
+ int index;
+ struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
+
+ if (!ops || !ops->is_mock_port(port->uport_dev))
+ devm_cxl_port_ras_setup(port);
+
+ put_cxl_mock_ops(index);
+}
+EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_port_ras_setup, "CXL");
+
struct cxl_dport *__wrap_cxl_add_dport_by_dev(struct cxl_port *port,
struct device *dport_dev)
{
--
2.34.1
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