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Message-ID: <8d91c98a99a0a1b368691a93141f4f14e5ece44c.camel@mediatek.com>
Date: Wed, 14 Jan 2026 06:39:24 +0000
From: Johnny-CC Chang (張晋嘉)
<Johnny-CC.Chang@...iatek.com>
To: "lukas@...ner.de" <lukas@...ner.de>
CC: Project_Global_Digits_Upstream_Group
<Project_Global_Digits_Upstream_Group@...iatek.com>, "AngeloGioacchino Del
Regno" <angelogioacchino.delregno@...labora.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-pci@...r.kernel.org"
<linux-pci@...r.kernel.org>, "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>, "bhelgaas@...gle.com"
<bhelgaas@...gle.com>, "matthias.bgg@...il.com" <matthias.bgg@...il.com>
Subject: Re: [PATCH] PCI: Mark Nvidia GB10 to avoid bus reset
On Tue, 2025-11-18 at 17:39 +0800, Johnny-CC Chang wrote:
> On Thu, 2025-11-13 at 10:39 +0100, Lukas Wunner wrote:
> > On Thu, Nov 13, 2025 at 04:44:06PM +0800, Johnny Chang wrote:
> > > Nvidia GB10 PCIe hosts will encounter problem occasionally
> > > after SBR(secondary bus reset) is applied.
> >
> > Could you elaborate what kinds of problems occur, how often they
> > occur, etc?
>
> There is about 1/1000 chance that after SBR is applied, any further
> access via this root port will be blocked and make system crash.
>
> Thanks,
>
> Johnny
I would like to update below description to replace original comment in
v1 patch, is this information sufficient?
--------
/*
* After SBR(secondary bus reset) is applied on an Nvidia GB10
* PCIe root port, there is 1/1000 chance that further requests
* via this root port will be blocked and cause system unstable.
*/
--------
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