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Message-ID: <8bf79979-0946-4ed9-b8d4-c442a6e54833@collabora.com>
Date: Wed, 14 Jan 2026 09:59:40 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Andy Shevchenko <andriy.shevchenko@...el.com>
Cc: jic23@...nel.org, dlechner@...libre.com, nuno.sa@...log.com,
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Subject: Re: [PATCH v7 05/10] nvmem: qcom-spmi-sdam: Migrate to
devm_spmi_subdevice_alloc_and_add()
Il 14/01/26 09:56, Andy Shevchenko ha scritto:
> On Wed, Jan 14, 2026 at 09:39:52AM +0100, AngeloGioacchino Del Regno wrote:
>> Some Qualcomm PMICs integrate a SDAM device, internally located in
>> a specific address range reachable through SPMI communication.
>>
>> Instead of using the parent SPMI device (the main PMIC) as a kind
>> of syscon in this driver, register a new SPMI sub-device for SDAM
>> and initialize its own regmap with this sub-device's specific base
>> address, retrieved from the devicetree.
>>
>> This allows to stop manually adding the register base address to
>> every R/W call in this driver, as this can be, and is now, handled
>> by the regmap API instead.
>
> ...
>
>> + struct regmap_config sdam_regmap_config = {
>> + .reg_bits = 16,
>> + .val_bits = 8,
>
>> + .max_register = 0x100,
>
> Are you sure? This might be a bad naming, but here max == the last accessible.
> I bet it has to be 0xff (but since the address is 16-bit it might be actually
> 257 registers, but sounds very weird).
>
Yes, I'm sure.
>> + .fast_io = true,
>> + };
>
> ...
>
>> + rc = of_property_read_u32(dev->of_node, "reg", &sdam_regmap_config.reg_base);
>
> Why not device_property_read_u32(dev, ...) ?
>
> ...
>
>> + sdam->regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev, &sdam_regmap_config);
>> + if (IS_ERR(sdam->regmap))
>> + return dev_err_probe(&pdev->dev, PTR_ERR(sdam->regmap),
>
> You have "dev".
>
>> + "Failed to get regmap handle\n");
>
For the other comments: Done in v8.
Cheers,
Angelo
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