linux-kernel - Re: [PATCH] PCI: Mark Nvidia GB10 to avoid bus reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20260115221130.GA888637@bhelgaas>
Date: Thu, 15 Jan 2026 16:11:30 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Johnny Chang <Johnny-CC.Chang@...iatek.com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org,
	Project_Global_Digits_Upstream_Group@...iatek.com,
	Lukas Wunner <lukas@...ner.de>, Jason Gunthorpe <jgg@...dia.com>,
	Alex Williamson <alex@...zbot.org>,
	Terje Bergstrom <tbergstrom@...dia.com>
Subject: Re: [PATCH] PCI: Mark Nvidia GB10 to avoid bus reset

On Thu, Nov 13, 2025 at 04:44:06PM +0800, Johnny Chang wrote:
> From: Johnny-CC Chang <Johnny-CC.Chang@...iatek.com>
> 
> Nvidia GB10 PCIe hosts will encounter problem occasionally
> after SBR(secondary bus reset) is applied.
> Enable NO_BUS_RESET quirk for Nvidia GB10 PCIe hosts.
> 
> Signed-off-by: Johnny-CC Chang <Johnny-CC.Chang@...iatek.com>

Applied with the commit log below to pci/virtualization for v6.20,
thanks!

  PCI: Mark Nvidia GB10 to avoid bus reset
  
  After asserting Secondary Bus Reset to downstream devices via a GB10 Root
  Port, the link may not retrain correctly, e.g., the link may retrain with a
  lower lane count or config accesses to downstream devices may fail.
  
  Prevent use of Secondary Bus Reset for devices below GB10.
  
  Signed-off-by: Johnny-CC Chang <Johnny-CC.Chang@...iatek.com>
  [bhelgaas: drop pci_ids.h update (only used once), update commit log]
  Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
  Link: https://patch.msgid.link/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com

> ---
>  drivers/pci/quirks.c    | 11 +++++++++++
>  include/linux/pci_ids.h |  2 ++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index b94264cd3833..12a10fa84c8a 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -3746,6 +3746,17 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
>  	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
>  }
>  
> +/*
> + * Nvidia GB10 PCIe hosts will encounter problem occasionally
> + * after SBR (secondary bus reset) is applied.
> + * SBR needs to be prevented for these PCIe hosts.
> + */
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GB10_GEN5_X4,
> +			 quirk_no_bus_reset);
> +
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GB10_GEN4_X1,
> +			 quirk_no_bus_reset);
> +
>  /*
>   * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
>   * prevented for those affected devices.
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 92ffc4373f6d..661dc1594213 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -1382,6 +1382,8 @@
>  #define PCI_DEVICE_ID_NVIDIA_GEFORCE_320M           0x08A0
>  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS     0x0AA2
>  #define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA	    0x0D85
> +#define PCI_DEVICE_ID_NVIDIA_GB10_GEN5_X4           0x22CE
> +#define PCI_DEVICE_ID_NVIDIA_GB10_GEN4_X1           0x22D0
>  
>  #define PCI_VENDOR_ID_IMS		0x10e0
>  #define PCI_DEVICE_ID_IMS_TT128		0x9128
> -- 
> 2.45.2
>