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Message-ID: <CAPVz0n3fwQNb2JozBx8G+r=txrENf1g3We5-P+sYJWepDJqU2Q@mail.gmail.com>
Date: Thu, 15 Jan 2026 09:45:21 +0200
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Mikko Perttunen <mperttunen@...dia.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Thierry Reding <thierry.reding@...il.com>,
Thierry Reding <treding@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>, Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Dmitry Osipenko <digetx@...il.com>, Charan Pedumuru <charan.pedumuru@...il.com>, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, dri-devel@...ts.freedesktop.org
Subject: Re: [PATCH v2 3/4 RESEND] gpu/drm: tegra: dsi: add support for Tegra20/Tegra30
чт, 15 січ. 2026 р. о 09:02 Mikko Perttunen <mperttunen@...dia.com> пише:
>
> On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> > Tegra20 and Tegra30 are fully compatible with existing tegra DSI driver
> > apart from clock configuration and PAD calibration which are addressed by
> > this patch.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> > ---
> > drivers/gpu/drm/tegra/drm.c | 2 +
> > drivers/gpu/drm/tegra/dsi.c | 88 ++++++++++++++++++++++++-------------
> > drivers/gpu/drm/tegra/dsi.h | 15 +++++++
> > 3 files changed, 74 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
> > index 4596073fe28f..5d64cd57e764 100644
> > --- a/drivers/gpu/drm/tegra/drm.c
> > +++ b/drivers/gpu/drm/tegra/drm.c
> > @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
> >
> > static const struct of_device_id host1x_drm_subdevs[] = {
> > { .compatible = "nvidia,tegra20-dc", },
> > + { .compatible = "nvidia,tegra20-dsi", },
> > { .compatible = "nvidia,tegra20-hdmi", },
> > { .compatible = "nvidia,tegra20-gr2d", },
> > { .compatible = "nvidia,tegra20-gr3d", },
> > { .compatible = "nvidia,tegra30-dc", },
> > + { .compatible = "nvidia,tegra30-dsi", },
> > { .compatible = "nvidia,tegra30-hdmi", },
> > { .compatible = "nvidia,tegra30-gr2d", },
> > { .compatible = "nvidia,tegra30-gr3d", },
> > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
> > index 8e80c7efe8b4..d079aa7d2a85 100644
> > --- a/drivers/gpu/drm/tegra/dsi.c
> > +++ b/drivers/gpu/drm/tegra/dsi.c
> > @@ -53,6 +53,10 @@ to_dsi_state(struct drm_connector_state *state)
> > return container_of(state, struct tegra_dsi_state, base);
> > }
> >
> > +struct tegra_dsi_config {
> > + u32 dsi_version;
>
> Rather than a dsi_version field, we should have something that describes the difference. e.g. 'bool has_multiple_pad_controls' being true for the "V1" hardware.
>
I used versioning from downstream dsi sources, where with addition of
Tegra114 support older DSI controller got v0 and newer v1, but if you
find 'has_multiple_pad_controls' more suitable I have no objections.
> > +};
> > +
> > struct tegra_dsi {
> > struct host1x_client client;
> > struct tegra_output output;
> > @@ -82,6 +86,8 @@ struct tegra_dsi {
> > /* for ganged-mode support */
> > struct tegra_dsi *master;
> > struct tegra_dsi *slave;
> > +
> > + const struct tegra_dsi_config *config;
> > };
> >
> > static inline struct tegra_dsi *
> > @@ -663,39 +669,46 @@ static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
> > {
> > u32 value;
> >
> > - value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
> > - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> > + if (dsi->config->dsi_version == TEGRA_DSI_V1) {
> > + /*
> > + * XXX Is this still needed? The module reset is deasserted right
> > + * before this function is called.
> > + */
> > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
> > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
> > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
> > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
> > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
> > +
> > + value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
> > + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> > +
> > + value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
> > + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
> > + DSI_PAD_OUT_CLK(0x0);
> > + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
> > +
> > + value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
> > + DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
> > + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
> > + } else {
> > + value = DSI_PAD_CONTROL_LPUPADJ(0x1) | DSI_PAD_CONTROL_LPDNADJ(0x1) |
> > + DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) |
> > + DSI_PAD_CONTROL_SLEWUPADJ(0x6) | DSI_PAD_CONTROL_PDIO(0) |
> > + DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0);
> > + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
> > + }
> >
> > return 0;
> > }
> >
> > static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
> > {
> > - u32 value;
> > int err;
> >
> > - /*
> > - * XXX Is this still needed? The module reset is deasserted right
> > - * before this function is called.
> > - */
> > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
> > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
> > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
> > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
> > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
> > -
> > /* start calibration */
> > tegra_dsi_pad_enable(dsi);
> >
> > - value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
> > - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
> > - DSI_PAD_OUT_CLK(0x0);
> > - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
> > -
> > - value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
> > - DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
> > - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
> > -
> > err = tegra_mipi_start_calibration(dsi->mipi);
> > if (err < 0)
> > return err;
> > @@ -1577,6 +1590,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
> > if (!dsi)
> > return -ENOMEM;
> >
> > + dsi->config = of_device_get_match_data(&pdev->dev);
> > dsi->output.dev = dsi->dev = &pdev->dev;
> > dsi->video_fifo_depth = 1920;
> > dsi->host_fifo_depth = 64;
> > @@ -1615,7 +1629,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
> > goto remove;
> > }
> >
> > - dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
> > + dsi->clk_lp = devm_clk_get_optional(&pdev->dev, "lp");
> > if (IS_ERR(dsi->clk_lp)) {
> > err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
> > "cannot get low-power clock\n");
> > @@ -1636,10 +1650,12 @@ static int tegra_dsi_probe(struct platform_device *pdev)
> > goto remove;
> > }
> >
> > - err = tegra_dsi_setup_clocks(dsi);
>
> > - if (err < 0) {
> > - dev_err(&pdev->dev, "cannot setup clocks\n");
> > - goto remove;
> > + if (dsi->config->dsi_version == TEGRA_DSI_V1) {
>
> And 'has_mux_parent_clk', perhaps? Not a very good name, if you come up with something better feel free to use it.
Noted
>
> I checked, and looks like Tegra30 in fact allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2, it is just not modelled in the clock driver. The same applies to all of Tegra114, 124, and 210, but only Tegra114 has it presently modelled as a mux whereas 124 and 210 have a gate. The TRMs for 124 and 210 specify that only PLL_D can be used in the mux bit documentation so the bit is probably dysfunctional on those chips.
>
> The correct solution, hence, I think is to have that config field, and it be false for Tegra20, 124, and 210; and true for Tegra30, and 114. Then implement the mux clock in the Tegra30 clock driver.
>
> However, I would settle for setting it to false for both Tegra20 and Tegra30 and leaving a comment next to the Tegra30 entry describing the situation (the mux clock is not currently modelled).
>
I clearly understand your point. I agree regarding setting it to false
for both Tegra20 and Tegra30 and leaving a comment for Tegra30, it
seems to be the optimal solution. Later on if there would be such
need, Tegra30 can get its mux too.
A little note regarding mux on Tegra124/210, it seems that bit is not
dysfunctional but behavior is intentional to diverge PLLD and D2 as
"internal" and "external" main display clock. At least this is what I
have concluded while working with Tegra display controller stuff.
> Cheers,
> Mikko
>
Thank you for your review!
Best regards,
Svyatoslav R.
> > + err = tegra_dsi_setup_clocks(dsi);
> > + if (err < 0) {
> > + dev_err(&pdev->dev, "cannot setup clocks\n");
> > + goto remove;
> > + }
> > }
> >
> > dsi->regs = devm_platform_ioremap_resource(pdev, 0);
> > @@ -1703,11 +1719,21 @@ static void tegra_dsi_remove(struct platform_device *pdev)
> > tegra_mipi_free(dsi->mipi);
> > }
> >
> > +static const struct tegra_dsi_config tegra20_dsi_config = {
> > + .dsi_version = TEGRA_DSI_V0,
> > +};
> > +
> > +static const struct tegra_dsi_config tegra114_dsi_config = {
> > + .dsi_version = TEGRA_DSI_V1,
> > +};
> > +
> > static const struct of_device_id tegra_dsi_of_match[] = {
> > - { .compatible = "nvidia,tegra210-dsi", },
> > - { .compatible = "nvidia,tegra132-dsi", },
> > - { .compatible = "nvidia,tegra124-dsi", },
> > - { .compatible = "nvidia,tegra114-dsi", },
> > + { .compatible = "nvidia,tegra210-dsi", .data = &tegra114_dsi_config },
> > + { .compatible = "nvidia,tegra132-dsi", .data = &tegra114_dsi_config },
> > + { .compatible = "nvidia,tegra124-dsi", .data = &tegra114_dsi_config },
> > + { .compatible = "nvidia,tegra114-dsi", .data = &tegra114_dsi_config },
> > + { .compatible = "nvidia,tegra30-dsi", .data = &tegra20_dsi_config },
> > + { .compatible = "nvidia,tegra20-dsi", .data = &tegra20_dsi_config },
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
> > diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h
> > index f39594e65e97..5049ec7813c7 100644
> > --- a/drivers/gpu/drm/tegra/dsi.h
> > +++ b/drivers/gpu/drm/tegra/dsi.h
> > @@ -95,6 +95,16 @@
> > #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
> > #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
> > #define DSI_PAD_CONTROL_0 0x4b
> > +/* DSI V0 */
> > +#define DSI_PAD_CONTROL_PULLDN_ENAB(x) (((x) & 0x1) << 28)
> > +#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24)
> > +#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20)
> > +#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19)
> > +#define DSI_PAD_CONTROL_PDIO_CLK(x) (((x) & 0x1) << 18)
> > +#define DSI_PAD_CONTROL_PDIO(x) (((x) & 0x3) << 16)
> > +#define DSI_PAD_CONTROL_LPUPADJ(x) (((x) & 0x3) << 14)
> > +#define DSI_PAD_CONTROL_LPDNADJ(x) (((x) & 0x3) << 12)
> > +/* DSI V1 */
> > #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
> > #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
> > #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
> > @@ -140,4 +150,9 @@ enum tegra_dsi_format {
> > TEGRA_DSI_FORMAT_24P,
> > };
> >
> > +enum tegra_dsi_version {
> > + TEGRA_DSI_V0,
> > + TEGRA_DSI_V1,
> > +};
> > +
> > #endif
> >
>
>
>
>
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