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Message-ID: <23752317.EfDdHjke4D@senjougahara>
Date: Thu, 15 Jan 2026 16:08:47 +0900
From: Mikko Perttunen <mperttunen@...dia.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>,
 Thierry Reding <thierry.reding@...il.com>,
 Thierry Reding <treding@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>,
 Prashant Gaikwad <pgaikwad@...dia.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
 Svyatoslav Ryhel <clamor95@...il.com>, Dmitry Osipenko <digetx@...il.com>,
 Charan Pedumuru <charan.pedumuru@...il.com>,
 Svyatoslav Ryhel <clamor95@...il.com>
Cc: devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
 dri-devel@...ts.freedesktop.org
Subject:
 Re: [PATCH v2 1/4 RESEND] clk: tegra20: reparent dsi clock to pll_d_out0

On Thursday, December 4, 2025 3:17 PM Svyatoslav Ryhel wrote:
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> Acked-by: Stephen Boyd <sboyd@...nel.org>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index bf9a9f8ddf62..9160f27a6cf0 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -801,9 +801,9 @@ static void __init tegra20_periph_clk_init(void)
>  	clks[TEGRA20_CLK_MC] = clk;
>  
>  	/* dsi */
> -	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
> -				    48, periph_clk_enb_refcnt);
> -	clk_register_clkdev(clk, NULL, "dsi");
> +	clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0,
> +					     clk_base, 0, TEGRA20_CLK_DSI,
> +					     periph_clk_enb_refcnt);
>  	clks[TEGRA20_CLK_DSI] = clk;
>  
>  	/* csus */
> 

Reviewed-by: Mikko Perttunen <mperttunen@...dia.com>




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