linux-kernel - Re: [PATCH 07/11] perf/amd/ibs: Support IBS_{FETCH|OP}

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Message-ID: <7a012575-bf92-4614-80e7-6bbe593f57cd@amd.com>
Date: Mon, 19 Jan 2026 18:30:12 +0530
From: Ravi Bangoria <ravi.bangoria@....com>
To: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
CC: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim
	<namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>, James Clark
	<james.clark@...aro.org>, <x86@...nel.org>,
	<linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>, "Manali
 Shukla" <manali.shukla@....com>, Santosh Shukla <santosh.shukla@....com>,
	Ananth Narayan <ananth.narayan@....com>, Sandipan Das <sandipan.das@....com>
Subject: Re: [PATCH 07/11] perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to
 eliminate RMW race

Hi Dapeng,

>>  static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
>>  {
>>  	setup_APIC_ibs();
>> +
>> +	if (ibs_caps & IBS_CAPS_DIS) {
>> +		/*
>> +		 * IBS enable sequence:
>> +		 *   CTL[En] = 1;
>> +		 *   CTL2[Dis] = 0;
>> +		 *
>> +		 * IBS disable sequence:
>> +		 *   CTL2[Dis] = 1;
>> +		 *
>> +		 * Set CTL2[Dis] when CPU comes up. This is needed to make
>> +		 * enable sequence effective.
>> +		 */
>> +		wrmsrq(MSR_AMD64_IBSFETCHCTL2, 1);
>> +		wrmsrq(MSR_AMD64_IBSOPCTL2, 1);
> 
> What does the BIT 0 of these 2 MSRs mean? Disable? Better define a macro
> instead of using the magic number "1". 

Right, those are disable bits. I'll replace those magic numbers with
IBS_FETCH_2_DIS and IBS_OP_2_DIS.

Thanks,
Ravi