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Message-ID: <CAHk-=wi2Y3MuMb+HMROL1+Jx8khu8QQnSX-_dmqTWX-kw7i8dw@mail.gmail.com>
Date: Mon, 19 Jan 2026 09:40:36 -0800
From: Linus Torvalds <torvalds@...ux-foundation.org>
To: Gary Guo <gary@...yguo.net>
Cc: Vladimir Kondratiev <Vladimir.Kondratiev@...ileye.com>, Paul Walmsley <pjw@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>, Will Deacon <will@...nel.org>,
Peter Zijlstra <peterz@...radead.org>, Boqun Feng <boqun.feng@...il.com>,
Mark Rutland <mark.rutland@....com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, Yury Norov <yury.norov@...il.com>,
Rasmus Villemoes <linux@...musvillemoes.dk>, Chao-ying Fu <cfu@...s.com>,
Aleksandar Rikalo <arikalo@...il.com>, Aleksa Paunovic <aleksa.paunovic@...cgroup.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>, "olof@...om.net" <olof@...om.net>
Subject: Re: [PATCH] riscv: support CPUs having only "zalrsc" but no "zaamo"
On Mon, 19 Jan 2026 at 09:17, Gary Guo <gary@...yguo.net> wrote:
>
> I'd be curious to know if any kind of performance evaluation has been done.
> atomic_inc is quite heavily used in the kernel.
LR/SC isn't generally a huge problem in itself - the problem is
typically that it requires a somewhat smart cache coherency to not get
into nasty "almost livelock" situations where heavy contention can
make things very unfair, and while the system on the whole makes
progress, some cores may end up starved.
That typically isn't seen unless you have lots of cores, though.
Of course, any CPU design that then left out AMO instructions in the
name of simplicity, probably *also* didn't put a lot of effort into
making the cache coherency have any kind of fairness guarantees.
So the platform is probably garbage for various other reasons.
Linus
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