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Message-ID: <20260120-lrsc-only-v2-0-a522e640d27d@mobileye.com>
Date: Tue, 20 Jan 2026 16:26:22 +0200
From: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
To: Paul Walmsley <pjw@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Will Deacon <will@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Boqun Feng <boqun.feng@...il.com>,
Mark Rutland <mark.rutland@....com>,
Gary Guo <gary@...yguo.net>,
Yury Norov <yury.norov@...il.com>,
Rasmus Villemoes <linux@...musvillemoes.dk>,
cfu@...ecomp.com,
torvalds@...ux-foundation.org,
olof@...om.net,
aleksa.paunovic@...cgroup.com,
arikalo@...il.com
Cc: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Vladimir.Kondratiev@...ileye.com
Subject: [PATCH v2 0/2] Support for Risc-V CPUs implementing LR/SC but not AMO
Primary goal is to support Mobileye eyeq7h automotive platform
based on MIPS P8700 CPU [1] having only "zalrsc" ISA extension but
not full "a".
Such platforms need userspace to be compiled with correct
"-march" flags to generate proper instructions for the atomic types
so there's not feasible to use universal userspace for it.
Thus there's no point to do same binary kernel suitable for both
"full A" and "LRSC only" platform types. Do a compile time
alternatives and require CONFIG_NONPORTABLE for this
[1] https://mips.com/products/hardware/p8700/
Patch 1 do most of work to provide compile-time LR/SC alternatives
for the AMO instructions
Patch 2 adjust tests for reported CPU extensions compatibility with
the code
Changes in v2: switch from dynamic atomic flavor resolution to
compile-time one.
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
---
Vladimir Kondratiev (2):
riscv: support ISA extensions "zaamo" and "zalrsc"
riscv: more accurate check for CPU atomics support
arch/riscv/Kconfig | 19 ++++++++++++++
arch/riscv/Makefile | 16 ++++++++----
arch/riscv/include/asm/atomic.h | 56 +++++++++++++++++++++++++++++++++++++++-
arch/riscv/include/asm/bitops.h | 48 ++++++++++++++++++++++++++++++++++
arch/riscv/include/asm/cmpxchg.h | 18 +++++++++++++
arch/riscv/include/asm/futex.h | 52 +++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/cpu.c | 22 +++++++++++++---
arch/riscv/kernel/entry.S | 9 +++++++
arch/riscv/kernel/head.S | 18 +++++++++++++
9 files changed, 248 insertions(+), 10 deletions(-)
---
base-commit: 7d0a66e4bb9081d75c82ec4957c50034cb0ea449
change-id: 20260120-lrsc-only-cc06422f5bb1
Best regards,
--
Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
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