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Message-Id: <20260120144436.233998-2-kanadenady@gmail.com>
Date: Tue, 20 Jan 2026 22:44:35 +0800
From: Nadi Ke <kanadenady@...il.com>
To: sboyd@...nel.org,
mturquette@...libre.com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
orsonzhai@...il.com,
baolin.wang@...ux.alibaba.com,
zhang.lyra@...il.com
Cc: linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Nadi Ke <kanadenady@...il.com>
Subject: [PATCH v1 1/2] dt-bindings: clock: sprd: Add SC9832E clock controller
Add device tree bindings for the Unisoc SC9832E Clock Control Unit.
Signed-off-by: Nadi Ke <kanadenady@...il.com>
---
.../bindings/clock/sprd,sc9832e-clk.yaml | 129 ++++++++++++
include/dt-bindings/clock/sprd,sc9832e-clk.h | 187 ++++++++++++++++++
2 files changed, 316 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
create mode 100644 include/dt-bindings/clock/sprd,sc9832e-clk.h
diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
new file mode 100644
index 000000000..82efd2493
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sprd,sc9832e-clk.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2026 Nadi Ke <kanadenady@...il.com>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sprd,sc9832e-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc SC9832E Clock Control Unit
+
+maintainers:
+ - Orson Zhai <orsonzhai@...il.com>
+ - Baolin Wang <baolin.wang7@...il.com>
+ - Chunyan Zhang <zhang.lyra@...il.com>
+ - Nadi Ke <kanadenady@...il.com>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - sprd,sc9832e-ap-clk
+ - sprd,sc9832e-aon-clk
+ - sprd,sc9832e-apahb-gate
+ - sprd,sc9832e-pmu-gate
+ - sprd,sc9832e-aonapb-gate
+ - sprd,sc9832e-apapb-gate
+ - sprd,sc9832e-pll
+ - sprd,sc9832e-mpll
+ - sprd,sc9832e-dpll
+ - sprd,sc9832e-rpll
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+ description: |
+ The input parent clock(s) phandle for this clock, only list fixed
+ clocks which are declared in devicetree.
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9832e-ap-clk
+ then:
+ required:
+ - reg
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: ext-26m
+ - const: ext-1m
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9832e-pmu-gate
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: ext-26m
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: sprd,sc9832e-aon-clk
+ then:
+ required:
+ - reg
+
+description: |
+ Unisoc SC9832E Clock Control Unit.
+ Other SC9832E clock nodes should be the child of a syscon node with
+ compatible: "sprd,sc9832e-glbregs", "syscon", "simple-mfd".
+ The 'reg' property is also required if there is a sub-range of registers.
+
+additionalProperties: false
+
+examples:
+ - |
+ /* AP Clock Controller */
+ ap_clk: clock-controller@...00000 {
+ compatible = "sprd,sc9832e-ap-clk";
+ reg = <0x21500000 0x1000>;
+ clocks = <&ext_26m>, <&ext_1m>;
+ clock-names = "ext-26m", "ext-1m";
+ #clock-cells = <1>;
+ };
+
+ - |
+ /* PMU Gate Controller inside Syscon */
+ syscon@...b0000 {
+ compatible = "sprd,sc9832e-glbregs", "syscon", "simple-mfd";
+ reg = <0x402b0000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x402b0000 0x4000>;
+
+ pmu_gate: pmu-gate@0 {
+ compatible = "sprd,sc9832e-pmu-gate";
+ reg = <0x0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ #clock-cells = <1>;
+ };
+ };
+
+...
diff --git a/include/dt-bindings/clock/sprd,sc9832e-clk.h b/include/dt-bindings/clock/sprd,sc9832e-clk.h
new file mode 100644
index 000000000..6eff6a82b
--- /dev/null
+++ b/include/dt-bindings/clock/sprd,sc9832e-clk.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Unisoc SC9832E platform clocks
+ *
+ * Copyright (C) 2015 Spreadtrum, Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SC9832E_H_
+#define _DT_BINDINGS_CLK_SC9832E_H_
+
+#define CLK_ISPPLL_GATE 0
+#define CLK_MPLL_GATE 1
+#define CLK_DPLL_GATE 2
+#define CLK_LPLL_GATE 3
+#define CLK_GPLL_GATE 4
+#define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1)
+
+#define CLK_TWPLL 0
+#define CLK_TWPLL_768M 1
+#define CLK_TWPLL_384M 2
+#define CLK_TWPLL_192M 3
+#define CLK_TWPLL_96M 4
+#define CLK_TWPLL_48M 5
+#define CLK_TWPLL_24M 6
+#define CLK_TWPLL_12M 7
+#define CLK_TWPLL_512M 8
+#define CLK_TWPLL_256M 9
+#define CLK_TWPLL_128M 10
+#define CLK_TWPLL_64M 11
+#define CLK_TWPLL_307M2 12
+#define CLK_TWPLL_219M4 13
+#define CLK_TWPLL_170M6 14
+#define CLK_TWPLL_153M6 15
+#define CLK_TWPLL_76M8 16
+#define CLK_TWPLL_51M2 17
+#define CLK_TWPLL_38M4 18
+#define CLK_TWPLL_19M2 19
+#define CLK_LPLL 20
+#define CLK_LPLL_409M6 21
+#define CLK_LPLL_245M76 22
+#define CLK_GPLL 23
+#define CLK_ISPPLL 24
+#define CLK_ISPPLL_468M 25
+#define CLK_PLL_NUM (CLK_ISPPLL_468M + 1)
+
+#define CLK_MPLL 0
+#define CLK_MPLL_50M 1
+#define CLK_MPLL_NUM (CLK_MPLL_50M + 1)
+
+#define CLK_DPLL 0
+#define CLK_DPLL_40M 1
+#define CLK_DPLL_NUM (CLK_DPLL_40M + 1)
+
+#define CLK_AUDIO_GATE 0
+#define CLK_RPLL 1
+#define CLK_RPLL_390M 2
+#define CLK_RPLL_260M 3
+#define CLK_RPLL_195M 4
+#define CLK_RPLL_26M 5
+#define CLK_RPLL_NUM (CLK_RPLL_26M + 1)
+
+#define CLK_DSI_EB 0
+#define CLK_DISPC_EB 1
+#define CLK_VSP_EB 2
+#define CLK_GSP_EB 3
+#define CLK_OTG_EB 4
+#define CLK_DMA_PUB_EB 5
+#define CLK_CE_PUB_EB 6
+#define CLK_AHB_CKG_EB 7
+#define CLK_SDIO0_EB 8
+#define CLK_SDIO1_EB 9
+#define CLK_NANDC_EB 10
+#define CLK_EMMC_EB 11
+#define CLK_SPINLOCK_EB 12
+#define CLK_CE_EFUSE_EB 13
+#define CLK_EMMC_32K_EB 14
+#define CLK_SDIO0_32K_EB 15
+#define CLK_SDIO1_32K_EB 16
+#define CLK_AP_AHB_GATE_NUM (CLK_SDIO1_32K_EB + 1)
+
+#define CLK_ADC_EB 0
+#define CLK_FM_EB 1
+#define CLK_TPC_EB 2
+#define CLK_GPIO_EB 3
+#define CLK_PWM0_EB 4
+#define CLK_PWM1_EB 5
+#define CLK_PWM2_EB 6
+#define CLK_PWM3_EB 7
+#define CLK_KPD_EB 8
+#define CLK_AON_SYST_EB 9
+#define CLK_AP_SYST_EB 10
+#define CLK_AON_TMR_EB 11
+#define CLK_AP_TMR0_EB 12
+#define CLK_EFUSE_EB 13
+#define CLK_EIC_EB 14
+#define CLK_INTC_EB 15
+#define CLK_ADI_EB 16
+#define CLK_AUDIF_EB 17
+#define CLK_AUD_EB 18
+#define CLK_VBC_EB 19
+#define CLK_PIN_EB 20
+#define CLK_IPI_EB 21
+#define CLK_SPLK_EB 22
+#define CLK_AP_WDG_EB 23
+#define CLK_MM_EB 24
+#define CLK_AON_APB_CKG_EB 25
+#define CLK_GPU_EB 26
+#define CLK_CA7_TS0_EB 27
+#define CLK_CA7_DAP_EB 28
+#define CLK_AON_APB_GATE_NUM (CLK_CA7_DAP_EB + 1)
+
+#define CLK_AP_APB 0
+#define CLK_NANDC_ECC 1
+#define CLK_OTG_REF 2
+#define CLK_OTG_UTMI 3
+#define CLK_UART1 4
+#define CLK_I2C0 5
+#define CLK_I2C1 6
+#define CLK_I2C2 7
+#define CLK_I2C3 8
+#define CLK_I2C4 9
+#define CLK_SPI0 10
+#define CLK_SPI2 11
+#define CLK_HS_SPI 12
+#define CLK_IIS0 13
+#define CLK_CE 14
+#define CLK_NANDC_2X 15
+#define CLK_SDIO0_2X 16
+#define CLK_SDIO1_2X 17
+#define CLK_EMMC_2X 18
+#define CLK_VSP 19
+#define CLK_GSP 20
+#define CLK_DISPC0 21
+#define CLK_DISPC0_DPI 22
+#define CLK_DSI_RXESC 23
+#define CLK_DSI_LANEBYTE 24
+#define CLK_AP_CLK_NUM (CLK_DSI_LANEBYTE + 1)
+
+#define CLK_AON_APB 0
+#define CLK_ADI 1
+#define CLK_AUX0 2
+#define CLK_AUX1 3
+#define CLK_PWM0 4
+#define CLK_PWM1 5
+#define CLK_PWM2 6
+#define CLK_PWM3 7
+#define CLK_THM0 8
+#define CLK_THM1 9
+#define CLK_AUDIF 10
+#define CLK_AUD_IIS_DA0 11
+#define CLK_AUD_IIS_AD0 12
+#define CLK_CA53_DAP 13
+#define CLK_CA53_DMTCK 14
+#define CLK_CA53_TS 15
+#define CLK_DJTAG_TCK 16
+#define CLK_EMC_REF 17
+#define CLK_CSSYS 18
+#define CLK_TMR 19
+#define CLK_DSI_TEST 20
+#define CLK_SDPHY_APB 21
+#define CLK_AIO_APB 22
+#define CLK_DTCK_HW 23
+#define CLK_AP_MM 24
+#define CLK_AP_AXI 25
+#define CLK_NIC_GPU 26
+#define CLK_MM_ISP 27
+#define CLK_AON_CLK_NUM (CLK_MM_ISP + 1)
+
+#define CLK_SIM0_EB 0
+#define CLK_IIS0_EB 1
+#define CLK_APB_REG_EB 2
+#define CLK_SPI0_EB 3
+#define CLK_SPI2_EB 4
+#define CLK_I2C0_EB 5
+#define CLK_I2C1_EB 6
+#define CLK_I2C2_EB 7
+#define CLK_I2C3_EB 8
+#define CLK_I2C4_EB 9
+#define CLK_UART1_EB 10
+#define CLK_SIM0_32K_EB 11
+#define CLK_INTC0_EB 12
+#define CLK_INTC1_EB 13
+#define CLK_INTC2_EB 14
+#define CLK_INTC3_EB 15
+#define CLK_AP_APB_GATE_NUM (CLK_INTC3_EB + 1)
+
+#endif /* _DT_BINDINGS_CLK_SC9832E_H_ */
--
2.34.1
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