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Message-ID: <95b38a2a-d08f-4416-8492-f9c6767c61d6@kernel.org>
Date: Tue, 20 Jan 2026 18:31:01 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>,
Bjorn Andersson <andersson@...nel.org>, Linus Walleij <linusw@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Rajendra Nayak <rajendra.nayak@....qualcomm.com>,
Pankaj Patil <pankaj.patil@....qualcomm.com>,
Sibi Sankar <sibi.sankar@....qualcomm.com>
Cc: Bjorn Andersson <bjorn.andersson@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: qcom,glymur-tlmm: Document
Mahua TLMM block
On 20/01/2026 18:22, Gopikrishna Garmidi wrote:
> Document the pinctrl compatible for the Mahua SoC, a 12-core variant
> of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt
> for GPIO 155 instead of GPIO 143 as seen on Glymur.
>
> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>
> ---
> Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@....qualcomm.com>
Best regards,
Krzysztof
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