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Message-Id: <20260120-pinctrl-qcom-mahua-tlmm-v3-2-8809a09dc628@oss.qualcomm.com>
Date: Tue, 20 Jan 2026 09:22:51 -0800
From: Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>, Linus Walleij <linusw@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Rajendra Nayak <rajendra.nayak@....qualcomm.com>,
Pankaj Patil <pankaj.patil@....qualcomm.com>,
Sibi Sankar <sibi.sankar@....qualcomm.com>
Cc: Bjorn Andersson <bjorn.andersson@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>
Subject: [PATCH v3 2/2] pinctrl: qcom: glymur: Add Mahua TLMM support
Mahua TLMM block is identical to Glymur, but the PDC wake IRQ map
differs since PDC handles the interrupt for GPIO 155 instead of GPIO 143
as seen on Glymur. Hence add the Mahua-specific PDC map to the Glymur
TLMM driver.
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@....qualcomm.com>
---
drivers/pinctrl/qcom/pinctrl-glymur.c | 46 ++++++++++++++++++++++++++++++++---
1 file changed, 43 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c
index 335005084b6b..44f9745325b7 100644
--- a/drivers/pinctrl/qcom/pinctrl-glymur.c
+++ b/drivers/pinctrl/qcom/pinctrl-glymur.c
@@ -1729,6 +1729,26 @@ static const struct msm_gpio_wakeirq_map glymur_pdc_map[] = {
{ 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 },
};
+static const struct msm_gpio_wakeirq_map mahua_pdc_map[] = {
+ { 0, 116 }, { 2, 114 }, { 3, 115 }, { 4, 175 }, { 5, 176 },
+ { 7, 111 }, { 11, 129 }, { 13, 130 }, { 15, 112 }, { 19, 113 },
+ { 23, 187 }, { 27, 188 }, { 28, 121 }, { 29, 122 }, { 30, 136 },
+ { 31, 203 }, { 32, 189 }, { 34, 174 }, { 35, 190 }, { 36, 191 },
+ { 39, 124 }, { 43, 192 }, { 47, 193 }, { 51, 123 }, { 53, 133 },
+ { 55, 125 }, { 59, 131 }, { 64, 134 }, { 65, 150 }, { 66, 186 },
+ { 67, 132 }, { 68, 195 }, { 71, 135 }, { 75, 196 }, { 79, 197 },
+ { 83, 198 }, { 84, 181 }, { 85, 199 }, { 87, 200 }, { 91, 201 },
+ { 92, 182 }, { 93, 183 }, { 94, 184 }, { 95, 185 }, { 98, 202 },
+ { 105, 157 }, { 113, 128 }, { 121, 117 }, { 123, 118 }, { 125, 119 },
+ { 129, 120 }, { 131, 126 }, { 132, 160 }, { 133, 194 }, { 134, 127 },
+ { 141, 137 }, { 144, 138 }, { 145, 139 }, { 147, 140 }, { 148, 141 },
+ { 150, 146 }, { 151, 147 }, { 153, 148 }, { 154, 144 }, { 155, 159 },
+ { 156, 149 }, { 157, 151 }, { 163, 142 }, { 172, 143 }, { 181, 145 },
+ { 193, 161 }, { 196, 152 }, { 203, 177 }, { 208, 178 }, { 215, 162 },
+ { 217, 153 }, { 220, 154 }, { 221, 155 }, { 228, 179 }, { 230, 180 },
+ { 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 },
+};
+
static const struct msm_pinctrl_soc_data glymur_tlmm = {
.pins = glymur_pins,
.npins = ARRAY_SIZE(glymur_pins),
@@ -1742,14 +1762,34 @@ static const struct msm_pinctrl_soc_data glymur_tlmm = {
.egpio_func = 11,
};
+static const struct msm_pinctrl_soc_data mahua_tlmm = {
+ .pins = glymur_pins,
+ .npins = ARRAY_SIZE(glymur_pins),
+ .functions = glymur_functions,
+ .nfunctions = ARRAY_SIZE(glymur_functions),
+ .groups = glymur_groups,
+ .ngroups = ARRAY_SIZE(glymur_groups),
+ .ngpios = 251,
+ .wakeirq_map = mahua_pdc_map,
+ .nwakeirq_map = ARRAY_SIZE(mahua_pdc_map),
+ .egpio_func = 11,
+};
+
static const struct of_device_id glymur_tlmm_of_match[] = {
- { .compatible = "qcom,glymur-tlmm", },
- { }
+ { .compatible = "qcom,glymur-tlmm", .data = &glymur_tlmm },
+ { .compatible = "qcom,mahua-tlmm", .data = &mahua_tlmm },
+ { },
};
static int glymur_tlmm_probe(struct platform_device *pdev)
{
- return msm_pinctrl_probe(pdev, &glymur_tlmm);
+ const struct msm_pinctrl_soc_data *data;
+
+ data = of_device_get_match_data(&pdev->dev);
+ if (!data)
+ return -ENODEV;
+
+ return msm_pinctrl_probe(pdev, data);
}
static struct platform_driver glymur_tlmm_driver = {
--
2.34.1
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