linux-kernel - RE: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <TY3PR01MB113464D31C247317F76992AEA8696A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Wed, 21 Jan 2026 13:15:04 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: geert <geert@...ux-m68k.org>, biju.das.au <biju.das.au@...il.com>
CC: magnus.damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Prabhakar
 Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: RE: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L
 SoC

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 21 January 2026 13:05
> Subject: Re: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
> 
> Hi Biju,
> 
> On Tue, 20 Jan 2026 at 13:52, Biju <biju.das.au@...il.com> wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > Add the initial DTSI for the RZ/G3L SoC.
> > The files in this commit have the following meaning:
> >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> >
> > Added place holders to reuse the code for Renesas SMARC II carrier
> > board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > @@ -0,0 +1,219 @@
> 
> > +       soc: soc {
> > +               compatible = "simple-bus";
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               scif0: serial@...ac000 {
> > +                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
> > +                       reg = <0 0x100ac000 0 0x400>;
> > +                       interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "eri", "rxi", "txi",
> > +                                         "bri", "dri", "tei";
> > +                       clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
> > +                       clock-names = "fck";
> > +                       power-domains = <&cpg>;
> > +                       resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c0: i2c@...ae000 {
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       reg = <0 0x100AE000 0 0x400>;
> > +                       /* placeholder */
> > +               };
> > +
> > +               canfd: can@...c0000 {
> > +                       reg = <0 0x100c0000 0 0x20000>;
> > +                       /* placeholder */
> > +               };
> > +
> 
> Early feedback: depending on when this goes upstream, we may need a few more:
> 
> +               ohci0: usb@...10000 {
> +                       /* placeholder */
> +               };
> +
> +               ohci1: usb@...90000 {
> +                       /* placeholder */
> +               };
> +
> +               ehci0: usb@...10100 {
> +                       /* placeholder */
> +               };
> +
> +               ehci1: usb@...90100 {
> +                       /* placeholder */
> +               };
> +
> +               hsusb: usb@...30000 {
> +                       /* placeholder */
> +               };
> +
> +               pcie: pcie@...40000 {
> +                       /* placeholder */
> +               };

OK, I will keep an eye on these patch series.

Cheers,
Biju