linux-kernel - Re: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

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Message-ID: <CAMuHMdVvtDs3xKwMODJ=8gHr4qWt8Lw76WNd-kPyDVNyV3xUEA@mail.gmail.com>
Date: Wed, 21 Jan 2026 14:05:16 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Biju <biju.das.au@...il.com>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Biju Das <biju.das.jz@...renesas.com>, linux-renesas-soc@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

Hi Biju,

On Tue, 20 Jan 2026 at 13:52, Biju <biju.das.au@...il.com> wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
>
> Add the initial DTSI for the RZ/G3L SoC.
> The files in this commit have the following meaning:
>   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
>   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
>
> Added place holders to reuse the code for Renesas SMARC II carrier
> board.
>
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -0,0 +1,219 @@

> +       soc: soc {
> +               compatible = "simple-bus";
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               scif0: serial@...ac000 {
> +                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
> +                       reg = <0 0x100ac000 0 0x400>;
> +                       interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "eri", "rxi", "txi",
> +                                         "bri", "dri", "tei";
> +                       clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
> +                       clock-names = "fck";
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
> +                       status = "disabled";
> +               };
> +
> +               i2c0: i2c@...ae000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0 0x100AE000 0 0x400>;
> +                       /* placeholder */
> +               };
> +
> +               canfd: can@...c0000 {
> +                       reg = <0 0x100c0000 0 0x20000>;
> +                       /* placeholder */
> +               };
> +

Early feedback: depending on when this goes upstream, we may
need a few more:

+               ohci0: usb@...10000 {
+                       /* placeholder */
+               };
+
+               ohci1: usb@...90000 {
+                       /* placeholder */
+               };
+
+               ehci0: usb@...10100 {
+                       /* placeholder */
+               };
+
+               ehci1: usb@...90100 {
+                       /* placeholder */
+               };
+
+               hsusb: usb@...30000 {
+                       /* placeholder */
+               };
+
+               pcie: pcie@...40000 {
+                       /* placeholder */
+               };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds