linux-kernel - Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of dw_pcie_wait_for

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Message-ID: <kxppi2denhw3eriam2ryevjdebsjryeggzxbvtftr3ygd4jdzu@ah73wocpvmwj>
Date: Wed, 21 Jan 2026 21:17:21 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Niklas Cassel <cassel@...nel.org>
Cc: Shawn Lin <shawn.lin@...k-chips.com>, 
	Jingoo Han <jingoohan1@...il.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>, 
	Krzysztof Wilczyński <kwilczynski@...nel.org>, Rob Herring <robh@...nel.org>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org, 
	vincent.guittot@...aro.org, zhangsenchuan@...incomputing.com, dlemoal@...nel.org, 
	manivannan.sadhasivam@....qualcomm.com
Subject: Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of
 dw_pcie_wait_for_link() API

On Wed, Jan 21, 2026 at 02:22:17PM +0100, Niklas Cassel wrote:
> Hello Shawn,
> 
> On Wed, Jan 21, 2026 at 08:45:39PM +0800, Shawn Lin wrote:
> > 在 2026/01/02 星期五 20:01, Niklas Cassel 写道:
> > 
> > Hi Niklas,
> > 
> > Sorry for chiming in on this so late. There is a register called
> > PCIE_CLIENT_GENERAL_DEBUG_CON you may find on RK3588 TRM, you could
> > hold LTSSM on EP side in DETECT_QUIET before enabling trainning, by
> > setting BIT(6). And when EP side is ready to go, just clear BIT(6),
> > so the link is able to be established and host side can rescan to
> > find the EP properly.
> 
> Thank you for the suggestion.
> 
> Reading the register description of this debug control register.
> For as log as sd_hold_ltssm is set, the controller stays in the
> current LTSSM.
> 
> We could probably set this on the EP side, and only when starting
> the link do we clear this bit.
> 

I did consider this option before, but the problem with sd_hold_ltssm is that we
cannot predict the LTSSM state when the hold happens i.e., it will only hold
onto the current LTSSM state at the point of set, which might not be DETECT all
the time.

> However, I think that Mani's current proposal:
> https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dwc&id=01d16b8afb7afcc17f999f8b4a9b9cfe6c6fae71
> 
> 
> Will work with more controllers running in EP mode, not just rk3588.
> 
> Also, when powering on both boards at the same time, it is possible that
> the host side driver gets probed before the EP side.
> If the EP side driver has not been probed to set bit sd_hold_ltssm,
> the host will still see a load connected, but link training will fail,
> so it will still jump to Poll.Compliance.
> 

Exactly. By the time the hold happens, LTSSM could've moved to POLL states.

- Mani

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