linux-kernel - Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of dw_pcie_wait_for

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Message-ID: <ea1b977e-069d-4084-9bf4-d5bd8cd273d5@rock-chips.com>
Date: Thu, 22 Jan 2026 11:37:23 +0800
From: Shawn Lin <shawn.lin@...k-chips.com>
To: Niklas Cassel <cassel@...nel.org>
Cc: shawn.lin@...k-chips.com, Jingoo Han <jingoohan1@...il.com>,
 Manivannan Sadhasivam <mani@...nel.org>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kwilczynski@...nel.org>,
 Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
 linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
 vincent.guittot@...aro.org, zhangsenchuan@...incomputing.com,
 dlemoal@...nel.org, manivannan.sadhasivam@....qualcomm.com
Subject: Re: [PATCH v3 0/4] PCI: dwc: Rework the error handling of
 dw_pcie_wait_for_link() API



在 2026/01/21 星期三 21:22, Niklas Cassel 写道:
> Hello Shawn,
> 
> On Wed, Jan 21, 2026 at 08:45:39PM +0800, Shawn Lin wrote:
>> 在 2026/01/02 星期五 20:01, Niklas Cassel 写道:
>>
>> Hi Niklas,
>>
>> Sorry for chiming in on this so late. There is a register called
>> PCIE_CLIENT_GENERAL_DEBUG_CON you may find on RK3588 TRM, you could
>> hold LTSSM on EP side in DETECT_QUIET before enabling trainning, by
>> setting BIT(6). And when EP side is ready to go, just clear BIT(6),
>> so the link is able to be established and host side can rescan to
>> find the EP properly.
> 
> Thank you for the suggestion.
> 
> Reading the register description of this debug control register.
> For as log as sd_hold_ltssm is set, the controller stays in the
> current LTSSM.
> 
> We could probably set this on the EP side, and only when starting
> the link do we clear this bit.
> 
> However, I think that Mani's current proposal:
> https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dwc&id=01d16b8afb7afcc17f999f8b4a9b9cfe6c6fae71
> 
> 
> Will work with more controllers running in EP mode, not just rk3588.
> 
> Also, when powering on both boards at the same time, it is possible that
> the host side driver gets probed before the EP side.
> If the EP side driver has not been probed to set bit sd_hold_ltssm,
> the host will still see a load connected, but link training will fail,
> so it will still jump to Poll.Compliance.
> 
> So AFAICT, Mani's proposal:
> 1) Seems more generic.
> 2) Seems less racy.
> 


Just a update for what I found when playing with the IP
on this topic :)

1. enable PCIE_CAP_ENTER_COMPLIANCE bit for
LINK_CONTROL2_LINK_STATUS2_REG (PCIE_CAP + 0xa0), which forces the RP
into poll.compliance to sumulate this situation, even without devices
connected to the slot.

2. set DIRECT_POLCOMP_TO_DETECT(bit 9) and HOLD_LTSSM(bit 0) to
SD_CONTROL2_REG, and could find it's still in poll.compliance.


3. clr HOLD_LTSSM only, and the LTSMM back to detect.quite and stay
there.

This seems be able to work with dwc with RAS_DES support.But sure,
Mani's approach looks more stright forward and works for all
controllers.


> 
> Kind regards,
> Niklas
>