Message-ID: <20260121021913.GA1704619-robh@kernel.org>
Date: Tue, 20 Jan 2026 20:19:13 -0600
From: Rob Herring <robh@...nel.org>
To: Khristine Andreea Barbulescu <khristineandreea.barbulescu@....nxp.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
	Bartosz Golaszewski <brgl@...ev.pl>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Chester Lin <chester62515@...il.com>,
	Matthias Brugger <mbrugger@...e.com>,
	Ghennadi Procopciuc <ghennadi.procopciuc@....com>,
	Larisa Grigore <larisa.grigore@....com>, Lee Jones <lee@...nel.org>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Dong Aisheng <aisheng.dong@....com>, Jacky Bai <ping.bai@....com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	Alberto Ruiz <aruizrui@...hat.com>,
	Christophe Lizzi <clizzi@...hat.com>, devicetree@...r.kernel.org,
	Enric Balletbo <eballetb@...hat.com>,
	Eric Chanudet <echanude@...hat.com>, imx@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org, linux-gpio@...r.kernel.org,
	linux-kernel@...r.kernel.org, NXP S32 Linux Team <s32@....com>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	"Vincent Guittot devicetree @ vger . kernel . org" <vincent.guittot@...aro.org>
Subject: Re: [PATCH v8 01/10] dt-bindings: mfd: add support for the NXP SIUL2
 module

On Tue, Jan 20, 2026 at 01:59:13PM +0200, Khristine Andreea Barbulescu wrote:
> From: Andrei Stefanescu <andrei.stefanescu@....nxp.com>
> 
> Add the new dt-bindings for the NXP SIUL2 module which is a multi
> function device. It can export information about the SoC, configure
> the pinmux&pinconf for pins and it is also a GPIO controller with
> interrupt capability.
> 
> The existing SIUL2 pinctrl bindings becomes deprecated because it
> do not correctly describe the hardware. The SIUL2 module also
> offers GPIO control and exposes some registers which contain
> information about the SoC. Adding drivers for these functionalities
> would result in incorrect bindings with a lot of carved out regions
> for registers.
> 
> SIUL2 is a complex module that spans multiple register regions
> and provides several functions: pinmux and pin configuration
> through MSCR and IMCR registers, GPIO control through PGPDO
> and PGPDI registers, interrupt configuration registers,
> and SoC identification registers (MIDR).
> These registers are grouped under two instances, SIUL2_0 and
> SIUL2_1, and share the same functional context. The legacy
> binding models SIUL2 as a standalone pinctrl node, which only
> covers MSCR and IMCR.
> 
> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@....nxp.com>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@....nxp.com>
> ---
>  .../bindings/mfd/nxp,s32g2-siul2.yaml         | 165 ++++++++++++++++++
>  .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml      |   2 +
>  2 files changed, 167 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml

Doesn't look like this was tested...

> 
> diff --git a/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml b/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml
> new file mode 100644
> index 000000000000..ec743cf5f73e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml
> @@ -0,0 +1,165 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2024 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/nxp,s32g2-siul2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP S32 System Integration Unit Lite2 (SIUL2)
> +
> +maintainers:
> +  - Andrei Stefanescu <andrei.stefanescu@....nxp.com>
> +
> +description: |
> +  SIUL2 is a hardware block which implements pinmuxing,
> +  pinconf, GPIOs (some with interrupt capability) and
> +  registers which contain information about the SoC.
> +  There are generally two SIUL2 modules whose functionality
> +  is grouped together. For example interrupt configuration
> +  registers are part of SIUL2_1 even though interrupts are
> +  also available for SIUL2_0 pins.
> +
> +  The following register types are exported by SIUL2:
> +    - MIDR (MCU ID Register) - information related to the SoC
> +    - interrupt configuration registers
> +    - MSCR (Multiplexed Signal Configuration Register) - pinmuxing and pinconf
> +    - IMCR (Input Multiplexed Signal Configuration Register)- pinmuxing
> +    - PGPDO (Parallel GPIO Pad Data Out Register) - GPIO output value
> +    - PGPDI (Parallel GPIO Pad Data In Register) - GPIO input value
> +
> +  Most registers are 32bit wide with the exception of PGPDO/PGPDI which are
> +  16bit wide.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: nxp,s32g2-siul2
> +      - items:
> +          - enum:
> +              - nxp,s32g3-siul2
> +          - const: nxp,s32g2-siul2
> +
> +  gpio-controller: true
> +
> +  "#gpio-cells":
> +    const: 2
> +
> +  gpio-ranges:
> +    maxItems: 2
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  ranges:
> +    description: Address translation ranges for child nodes.
> +
> +
> +patternProperties:
> +  "^siul2_[0-1]$":

Don't use '_'.

> +    type: object
> +    description: SIUL2 hardware instances represented as syscon.
> +    properties:
> +      compatible:
> +        const: syscon

'syscon' alone is not allowed.

> +      reg:
> +        maxItems: 1

You have 'reg' so the node name should have unit-address.

However, there's not any real DT resources in this child node, so you 
should just drop it.

> +    required:
> +      - compatible
> +      - reg
> +
> +  "-hog(-[0-9]+)?$":
> +    required:
> +      - gpio-hog
> +
> +  "-pins$":
> +    type: object
> +    additionalProperties: false
> +
> +    patternProperties:
> +      "-grp[0-9]$":
> +        type: object
> +        allOf:
> +          - $ref: /schemas/pinctrl/pinmux-node.yaml#
> +          - $ref: /schemas/pinctrl/pincfg-node.yaml#
> +        description:
> +          Pinctrl node's client devices specify pin muxes using subnodes,
> +          which in turn use the standard properties below.
> +
> +        properties:
> +          pinmux:
> +            description: |
> +              An integer array for representing pinmux configurations of
> +              a device. Each integer consists of a PIN_ID and a 4-bit
> +              selected signal source(SSS) as IOMUX setting, which is
> +              calculated as: pinmux = (PIN_ID << 4 | SSS)
> +
> +          slew-rate:
> +            description: Supported slew rate based on Fmax values (MHz)
> +            enum: [83, 133, 150, 166, 208]
> +        required:
> +          - pinmux
> +
> +        unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +  - gpio-controller
> +  - "#gpio-cells"
> +  - gpio-ranges
> +  - interrupts
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    pinctrl@...9c000 {
> +      compatible = "nxp,s32g2-siul2";
> +      gpio-controller;
> +      #gpio-cells = <2>;
> +      gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>;
> +      interrupt-controller;
> +      #interrupt-cells = <2>;
> +      interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
> +      #address-cells = <1>;
> +      #size-cells = <1>;
> +      ranges;
> +
> +      siul2_0: siul2_0@...9c000 {
> +        compatible = "syscon";
> +        reg = <0x0 0x4009c000 0x0 0x179c>;
> +      };
> +
> +      siul2_1: siul2_1@...10000 {
> +        compatible = "syscon";
> +        reg = <0x0 0x44010000 0x0 0x17b0>;
> +      };
> +
> +      jtag-pins {
> +        jtag-grp0 {
> +          pinmux = <0x0>;
> +          input-enable;
> +          bias-pull-up;
> +          slew-rate = <166>;
> +        };
> +      };
> +    };
> +...
> diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
> index a24286e4def6..332397a21394 100644
> --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
> @@ -11,6 +11,8 @@ maintainers:
>    - Ghennadi Procopciuc <Ghennadi.Procopciuc@....nxp.com>
>    - Chester Lin <chester62515@...il.com>
>  
> +deprecated: true
> +

I don't really see why you can't just extend this binding with GPIO and 
interrupt provider properties.

Rob

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