linux-kernel - Re: [PATCH v5 3/9] riscv: csr: define vtype register elements

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Message-ID: <CAFTtA3MMgY5Nz_ZvQNfVijjTpk4w76B3keQjCLzftuFG05PDfg@mail.gmail.com>
Date: Wed, 21 Jan 2026 15:04:44 -0600
From: Andy Chiu <andybnac@...il.com>
To: Sergey Matyukevich <geomatsi@...il.com>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-kselftest@...r.kernel.org, Paul Walmsley <pjw@...nel.org>, 
	Palmer Dabbelt <palmer@...belt.com>, Alexandre Ghiti <alex@...ti.fr>, Oleg Nesterov <oleg@...hat.com>, 
	Shuah Khan <shuah@...nel.org>, Thomas Huth <thuth@...hat.com>, 
	Charlie Jenkins <charlie@...osinc.com>, Samuel Holland <samuel.holland@...ive.com>, 
	Joel Granados <joel.granados@...nel.org>, Conor Dooley <conor.dooley@...rochip.com>, 
	Yong-Xuan Wang <yongxuan.wang@...ive.com>, Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>
Subject: Re: [PATCH v5 3/9] riscv: csr: define vtype register elements

Hi Sergey,

On Sun, Dec 14, 2025 at 10:35 AM Sergey Matyukevich <geomatsi@...il.com> wrote:
>
> Define masks and shifts for vtype CSR according to the vector specs:
> - v0.7.1 used in early T-Head cores, known as xtheadvector in the kernel
> - v1.0
>
> Signed-off-by: Sergey Matyukevich <geomatsi@...il.com>

Reviewed-by: Andy Chiu <andybnac@...il.com>

Thanks for putting v0.7 together,
Andy