linux-kernel - Re: [PATCH v5 4/9] riscv: ptrace: validate input vector csr registers

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Message-ID: <CAFTtA3PPY-=bPJw1-iv56AQQ94saXZorC3rMM2Z4DwZJg4ruZg@mail.gmail.com>
Date: Wed, 21 Jan 2026 15:07:27 -0600
From: Andy Chiu <andybnac@...il.com>
To: Sergey Matyukevich <geomatsi@...il.com>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-kselftest@...r.kernel.org, Paul Walmsley <pjw@...nel.org>, 
	Palmer Dabbelt <palmer@...belt.com>, Alexandre Ghiti <alex@...ti.fr>, Oleg Nesterov <oleg@...hat.com>, 
	Shuah Khan <shuah@...nel.org>, Thomas Huth <thuth@...hat.com>, 
	Charlie Jenkins <charlie@...osinc.com>, Samuel Holland <samuel.holland@...ive.com>, 
	Joel Granados <joel.granados@...nel.org>, Conor Dooley <conor.dooley@...rochip.com>, 
	Yong-Xuan Wang <yongxuan.wang@...ive.com>, Heiko Stuebner <heiko@...ech.de>, Guo Ren <guoren@...nel.org>
Subject: Re: [PATCH v5 4/9] riscv: ptrace: validate input vector csr registers

Hi Sergey,

On Sun, Dec 14, 2025 at 10:35 AM Sergey Matyukevich <geomatsi@...il.com> wrote:
>
> Add strict validation for vector csr registers when setting them via
> ptrace:
> - reject attempts to set reserved bits or invalid field combinations
> - enforce strict VL checks against calculated VLMAX values
>
> Vector specs 0.7.1 and 1.0 allow normal applications to set candidate
> VL values and read back the hardware-adjusted results, see section 6
> for details. Disallow such flexibility in vector ptrace operations
> and strictly enforce valid VL input.
>
> The traced process may not update its saved vector context if no vector
> instructions execute between breakpoints. So the purpose of the strict
> ptrace approach is to make sure that debuggers maintain an accurate view
> of the tracee's vector context across multiple halt/resume debug cycles.
>
> Signed-off-by: Sergey Matyukevich <geomatsi@...il.com>

Reviewed-by: Andy Chiu <andybnac@...il.com>

Thanks,
Andy