lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <DFU4845TDZMC.1JL1V5A9FWWEL@cknow-tech.com>
Date: Wed, 21 Jan 2026 09:14:05 +0100
From: "Diederik de Haas" <diederik@...ow-tech.com>
To: "Chaoyi Chen" <kernel@...kyi.com>, "Andrew Lunn" <andrew@...n.ch>, "Rob
 Herring" <robh@...nel.org>, "Krzysztof Kozlowski" <krzk+dt@...nel.org>,
 "Conor Dooley" <conor+dt@...nel.org>, "Heiko Stuebner" <heiko@...ech.de>,
 "Alexey Charkov" <alchark@...il.com>, "Shawn Lin"
 <shawn.lin@...k-chips.com>, "Sebastian Reichel"
 <sebastian.reichel@...labora.com>, "Chaoyi Chen"
 <chaoyi.chen@...k-chips.com>, "Andy Yan" <andy.yan@...k-chips.com>,
 "Nicolas Frattaroli" <nicolas.frattaroli@...labora.com>, "Detlev Casanova"
 <detlev.casanova@...labora.com>, "Stephen Chen" <stephen@...xa.com>
Cc: <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
 <linux-rockchip@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] arm64: dts: rockchip: Change gmac phy-mode to
 rgmii-id for rk3576 evb1

On Wed Jan 21, 2026 at 4:15 AM CET, Chaoyi Chen wrote:
> From: Chaoyi Chen <chaoyi.chen@...k-chips.com>
>
> According to the description in the net documentation, PHY modes
> "rgmii", "rgmii-rxid" and "rgmii-txid" modes require the clock signal
> to be delayed on the PCB.
>
> The Rockchip platform has long used the above mentioned PHY modes and
> private delay prop to describe the internal IO delay settings of the
> chip, which is inconsistent with what is described in the documentation.
>
> Let's describe this part of the delay in the PHY and use the more
> reasonable "rgmii-id" mode.
>
> Signed-off-by: Chaoyi Chen <chaoyi.chen@...k-chips.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
> index c5584c26db52..3ee76bafafb5 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
> @@ -266,7 +266,7 @@ &combphy1_psu {
>  
>  &gmac0 {
>  	clock_in_out = "output";
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&rgmii_phy0>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&eth0m0_miim
> @@ -275,14 +275,13 @@ &eth0m0_rx_bus2
>  		     &eth0m0_rgmii_clk
>  		     &eth0m0_rgmii_bus
>  		     &ethm0_clk0_25m_out>;
> -	tx_delay = <0x21>;

This being '0x21' (not '0x20') ...

>  	status = "okay";
>  };
>  
>  &gmac1 {
>  	clock_in_out = "output";
>  	phy-handle = <&rgmii_phy1>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&eth1m0_miim
>  		     &eth1m0_tx_bus2
> @@ -290,7 +289,6 @@ &eth1m0_rx_bus2
>  		     &eth1m0_rgmii_clk
>  		     &eth1m0_rgmii_bus
>  		     &ethm0_clk1_25m_out>;
> -	tx_delay = <0x20>;
>  	status = "okay";
>  };
>  
> @@ -721,6 +719,7 @@ rgmii_phy0: ethernet-phy@1 {
>  		reset-assert-us = <20000>;
>  		reset-deassert-us = <100000>;
>  		reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
> +		tx-internal-delay-ps = <1950>;

... shouldn't this be higher?
0.0579 * 0x21 + 0.105 = 2.0157 (not sure how the rounding goes)

Cheers,
  Diederik

>  	};
>  };
>  
> @@ -737,6 +736,7 @@ rgmii_phy1: ethernet-phy@1 {
>  		reset-assert-us = <20000>;
>  		reset-deassert-us = <100000>;
>  		reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
> +		tx-internal-delay-ps = <1950>;
>  	};
>  };
>  


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ