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Message-ID:
<BN9PR18MB4251EED8DF6BD9B037A76F6BDB97A@BN9PR18MB4251.namprd18.prod.outlook.com>
Date: Thu, 22 Jan 2026 17:05:32 +0000
From: Elad Nachman <enachman@...vell.com>
To: Gregory CLEMENT <gregory.clement@...tlin.com>,
"Rob Herring (Arm)"
<robh@...nel.org>, Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth
<sebastian.hesselbarth@...il.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: RE: [EXTERNAL] Re: [PATCH] arm/arm64: dts: marvell: Drop unused .dtsi
Hi,
>
>
> From: Gregory CLEMENT <gregory.clement@...tlin.com>
> Sent: Thursday, January 22, 2026 6:10 PM
> To: Elad Nachman <enachman@...vell.com>; Rob Herring (Arm) <robh@...nel.org>; Andrew Lunn <andrew@...n.ch>; Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>; Krzysztof Kozlowski <krzk+dt@...nel.org>; Conor Dooley <conor+dt@...nel.org>
> Cc: linux-arm-kernel@...ts.infradead.org; devicetree@...r.kernel.org; linux-kernel@...r.kernel.org
> Subject: RE: [EXTERNAL] Re: [PATCH] arm/arm64: dts: marvell: Drop unused .dtsi
>
> Elad Nachman <enachman@ marvell. com> writes:
> > Hi,
> > >> >> >> From: Gregory CLEMENT <gregory. clement@ bootlin. com
> > >> Sent: Thursday, January 22, 2026 12: 01 PM
> >> To: Rob Herring (Arm) <robh@ kernel. org>;
> Elad Nachman <mailto:enachman@...vell.com> writes:
>
> > Hi,
> >
> >>
> >>
> >> From: Gregory CLEMENT <mailto:gregory.clement@...tlin.com>
> >> Sent: Thursday, January 22, 2026 12:01 PM
> >> To: Rob Herring (Arm) <mailto:robh@...nel.org>; Andrew Lunn <mailto:andrew@...n.ch>; Sebastian Hesselbarth <mailto:sebastian.hesselbarth@...il.com>; Krzysztof Kozlowski <mailto:krzk+dt@...nel.org>; Conor Dooley <mailto:conor+dt@...nel.org>; Elad Nachman <mailto:enachman@...vell.com>
> >> Cc: mailto:linux-arm-kernel@...ts.infradead.org; mailto:devicetree@...r.kernel.org; mailto:linux-kernel@...r.kernel.org
> >> Subject: [EXTERNAL] Re: [PATCH] arm/arm64: dts: marvell: Drop unused .dtsi
> >>
> >> Hello Rob,
> >> > These .dtsi files are not included anywhere in the tree and can't be
> >> > tested.
> >> > > Signed-off-by: Rob Herring (Arm) <robh@ kernel. org> > ---
> >> > arch/arm/boot/dts/marvell/armada-380. dtsi | 148
> >> Hello Rob,
> >>
> >> > These .dtsi files are not included anywhere in the tree and can't be
> >> > tested.
> >> >
> >> > Signed-off-by: Rob Herring (Arm) <mailto:robh@...nel.org>
> >> > ---
> >> > arch/arm/boot/dts/marvell/armada-380.dtsi | 148 ------------------
> >> > arch/arm64/boot/dts/marvell/armada-7020.dtsi | 10 --
> >> > arch/arm64/boot/dts/marvell/armada-8020.dtsi | 20 ---
> >> > .../boot/dts/marvell/armada-ap806-dual.dtsi | 60 -------
> >>
> >> For these ones I agree removing them
> >
> > armada-7020.dtsi uses armada-ap806-dual.dtsi
> > armada-7020.dtsi is used by several of our boards, I have submitted the following commit:
> > https://urldefense.proofpoint.com/v2/url?u=https-3A__lkml.org_lkml_2023_12_18_1024&d=DwIFaQ&c=nKjWec2b6R0mOyPaz7xtfQ&r=eTeNTLEK5-TxXczjOcKPhANIFtlB9pP4lq9qhdlFrwQ&m=50VLMgC6nXNq_pmjtWOf_YAQrQZy08qsFBzrbeyqKtEwW4HWmQTMfwARCcYNO-GL&s=uGlaWb2JGJxJYYlos8ADUdtG4B2NuAFAPVY5RdK7wrY&e=
> > But for some reason I did not get any response for it.
> > If we merge it, these two DTSI files (7020 and ap806-dual) will be
> > used.
>
>
> Even in the lore, it is not easy to find these emails, and indeed I
> missed them while I merged the previous series sent.
> Could you rebase and send it again ?
Done, watch for arm64: dts: a7k: add COM Express boards series...
Thanks...
>
> Gregory
>
> >
> >>
> >> > .../dts/marvell/cn9130-db-comexpress.dtsi | 96 ------------
> >>
> >> I am a bit more concerned about this one, as it really seems to be an
> >> existing module. I would like to get feedback from Elad Nachman, who
> >> submitted it, to find out if there is any dts board that can be
> >> submitted to keep this dtsi or, conversely, if we can indeed remove the
> >> dtsi.
> >
> > Currently we only have a Com-Express board for CN9131, so for now you can drop this one.
> >
> >>
> >> Gregory
> >>
> >> > 5 files changed, 334 deletions(-)
> >> > delete mode 100644 arch/arm/boot/dts/marvell/armada-380.dtsi
> >> > delete mode 100644 arch/arm64/boot/dts/marvell/armada-7020.dtsi
> >> > delete mode 100644 arch/arm64/boot/dts/marvell/armada-8020.dtsi
> >> > delete mode 100644 arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> >> > delete mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
> >> >
> >> > diff --git a/arch/arm/boot/dts/marvell/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi
> >> > deleted file mode 100644
> >> > index e94f22b0e9b5..000000000000
> >> > --- a/arch/arm/boot/dts/marvell/armada-380.dtsi
> >> > +++ /dev/null
> >> > @@ -1,148 +0,0 @@
> >> > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> > -/*
> >> > - * Device Tree Include file for Marvell Armada 380 SoC.
> >> > - *
> >> > - * Copyright (C) 2014 Marvell
> >> > - *
> >> > - * Lior Amsalem <mailto:alior@...vell.com>
> >> > - * Gregory CLEMENT <mailto:gregory.clement@...e-electrons.com>
> >> > - * Thomas Petazzoni <mailto:thomas.petazzoni@...e-electrons.com>
> >> > - */
> >> > -
> >> > -#include "armada-38x.dtsi"
> >> > -
> >> > -/ {
> >> > - model = "Marvell Armada 380 family SoC";
> >> > - compatible = "marvell,armada380";
> >> > -
> >> > - cpus {
> >> > - #address-cells = <1>;
> >> > - #size-cells = <0>;
> >> > - enable-method = "marvell,armada-380-smp";
> >> > -
> >> > - cpu@0 {
> >> > - device_type = "cpu";
> >> > - compatible = "arm,cortex-a9";
> >> > - reg = <0>;
> >> > - };
> >> > - };
> >> > -
> >> > - soc {
> >> > - internal-regs {
> >> > - pinctrl@...00 {
> >> > - compatible = "marvell,mv88f6810-pinctrl";
> >> > - };
> >> > - };
> >> > -
> >> > - pcie {
> >> > - compatible = "marvell,armada-370-pcie";
> >> > - status = "disabled";
> >> > - device_type = "pci";
> >> > -
> >> > - #address-cells = <3>;
> >> > - #size-cells = <2>;
> >> > -
> >> > - msi-parent = <&mpic>;
> >> > - bus-range = <0x00 0xff>;
> >> > -
> >> > - ranges =
> >> > - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
> >> > - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
> >> > - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
> >> > - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
> >> > - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
> >> > - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
> >> > - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
> >> > - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
> >> > - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
> >> > - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
> >> > -
> >> > - /* x1 port */
> >> > - pcie@1,0 {
> >> > - device_type = "pci";
> >> > - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
> >> > - reg = <0x0800 0 0 0 0>;
> >> > - #address-cells = <3>;
> >> > - #size-cells = <2>;
> >> > - interrupt-names = "intx";
> >> > - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> >> > - #interrupt-cells = <1>;
> >> > - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> >> > - 0x81000000 0 0 0x81000000 0x1 0 1 0>;
> >> > - bus-range = <0x00 0xff>;
> >> > - interrupt-map-mask = <0 0 0 7>;
> >> > - interrupt-map = <0 0 0 1 &pcie1_intc 0>,
> >> > - <0 0 0 2 &pcie1_intc 1>,
> >> > - <0 0 0 3 &pcie1_intc 2>,
> >> > - <0 0 0 4 &pcie1_intc 3>;
> >> > - marvell,pcie-port = <0>;
> >> > - marvell,pcie-lane = <0>;
> >> > - clocks = <&gateclk 8>;
> >> > - status = "disabled";
> >> > -
> >> > - pcie1_intc: interrupt-controller {
> >> > - interrupt-controller;
> >> > - #interrupt-cells = <1>;
> >> > - };
> >> > - };
> >> > -
> >> > - /* x1 port */
> >> > - pcie@2,0 {
> >> > - device_type = "pci";
> >> > - assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
> >> > - reg = <0x1000 0 0 0 0>;
> >> > - #address-cells = <3>;
> >> > - #size-cells = <2>;
> >> > - interrupt-names = "intx";
> >> > - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> >> > - #interrupt-cells = <1>;
> >> > - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
> >> > - 0x81000000 0 0 0x81000000 0x2 0 1 0>;
> >> > - bus-range = <0x00 0xff>;
> >> > - interrupt-map-mask = <0 0 0 7>;
> >> > - interrupt-map = <0 0 0 1 &pcie2_intc 0>,
> >> > - <0 0 0 2 &pcie2_intc 1>,
> >> > - <0 0 0 3 &pcie2_intc 2>,
> >> > - <0 0 0 4 &pcie2_intc 3>;
> >> > - marvell,pcie-port = <1>;
> >> > - marvell,pcie-lane = <0>;
> >> > - clocks = <&gateclk 5>;
> >> > - status = "disabled";
> >> > -
> >> > - pcie2_intc: interrupt-controller {
> >> > - interrupt-controller;
> >> > - #interrupt-cells = <1>;
> >> > - };
> >> > - };
> >> > -
> >> > - /* x1 port */
> >> > - pcie@3,0 {
> >> > - device_type = "pci";
> >> > - assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
> >> > - reg = <0x1800 0 0 0 0>;
> >> > - #address-cells = <3>;
> >> > - #size-cells = <2>;
> >> > - interrupt-names = "intx";
> >> > - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> >> > - #interrupt-cells = <1>;
> >> > - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
> >> > - 0x81000000 0 0 0x81000000 0x3 0 1 0>;
> >> > - bus-range = <0x00 0xff>;
> >> > - interrupt-map-mask = <0 0 0 7>;
> >> > - interrupt-map = <0 0 0 1 &pcie3_intc 0>,
> >> > - <0 0 0 2 &pcie3_intc 1>,
> >> > - <0 0 0 3 &pcie3_intc 2>,
> >> > - <0 0 0 4 &pcie3_intc 3>;
> >> > - marvell,pcie-port = <2>;
> >> > - marvell,pcie-lane = <0>;
> >> > - clocks = <&gateclk 6>;
> >> > - status = "disabled";
> >> > -
> >> > - pcie3_intc: interrupt-controller {
> >> > - interrupt-controller;
> >> > - #interrupt-cells = <1>;
> >> > - };
> >> > - };
> >> > - };
> >> > - };
> >> > -};
> >> > diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
> >> > deleted file mode 100644
> >> > index 570f901b4f4a..000000000000
> >> > --- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
> >> > +++ /dev/null
> >> > @@ -1,10 +0,0 @@
> >> > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> > -/*
> >> > - * Copyright (C) 2016 Marvell Technology Group Ltd.
> >> > - *
> >> > - * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
> >> > - * one CP110.
> >> > - */
> >> > -
> >> > -#include "armada-ap806-dual.dtsi"
> >> > -#include "armada-70x0.dtsi"
> >> > diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
> >> > deleted file mode 100644
> >> > index b6fc18876093..000000000000
> >> > --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
> >> > +++ /dev/null
> >> > @@ -1,20 +0,0 @@
> >> > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> > -/*
> >> > - * Copyright (C) 2016 Marvell Technology Group Ltd.
> >> > - *
> >> > - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
> >> > - * two CP110.
> >> > - */
> >> > -
> >> > -#include "armada-ap806-dual.dtsi"
> >> > -#include "armada-80x0.dtsi"
> >> > -
> >> > -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
> >> > - * in CP master is not connected (by package) to the oscillator. So
> >> > - * disable it. However, the RTC clock in CP slave is connected to the
> >> > - * oscillator so this one is let enabled.
> >> > - */
> >> > -
> >> > -&cp0_rtc {
> >> > - status = "disabled";
> >> > -};
> >> > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> >> > deleted file mode 100644
> >> > index 82f4dedfc25e..000000000000
> >> > --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> >> > +++ /dev/null
> >> > @@ -1,60 +0,0 @@
> >> > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> > -/*
> >> > - * Copyright (C) 2016 Marvell Technology Group Ltd.
> >> > - *
> >> > - * Device Tree file for Marvell Armada AP806.
> >> > - */
> >> > -
> >> > -#include "armada-ap806.dtsi"
> >> > -
> >> > -/ {
> >> > - cpus {
> >> > - #address-cells = <1>;
> >> > - #size-cells = <0>;
> >> > -
> >> > - cpu0: cpu@0 {
> >> > - device_type = "cpu";
> >> > - compatible = "arm,cortex-a72";
> >> > - reg = <0x000>;
> >> > - enable-method = "psci";
> >> > - #cooling-cells = <2>;
> >> > - clocks = <&cpu_clk 0>;
> >> > - i-cache-size = <0xc000>;
> >> > - i-cache-line-size = <64>;
> >> > - i-cache-sets = <256>;
> >> > - d-cache-size = <0x8000>;
> >> > - d-cache-line-size = <64>;
> >> > - d-cache-sets = <256>;
> >> > - next-level-cache = <&l2>;
> >> > - };
> >> > - cpu1: cpu@1 {
> >> > - device_type = "cpu";
> >> > - compatible = "arm,cortex-a72";
> >> > - reg = <0x001>;
> >> > - enable-method = "psci";
> >> > - #cooling-cells = <2>;
> >> > - clocks = <&cpu_clk 0>;
> >> > - i-cache-size = <0xc000>;
> >> > - i-cache-line-size = <64>;
> >> > - i-cache-sets = <256>;
> >> > - d-cache-size = <0x8000>;
> >> > - d-cache-line-size = <64>;
> >> > - d-cache-sets = <256>;
> >> > - next-level-cache = <&l2>;
> >> > - };
> >> > -
> >> > - l2: l2-cache {
> >> > - compatible = "cache";
> >> > - cache-size = <0x80000>;
> >> > - cache-line-size = <64>;
> >> > - cache-sets = <512>;
> >> > - cache-level = <2>;
> >> > - cache-unified;
> >> > - };
> >> > - };
> >> > -
> >> > - thermal-zones {
> >> > - /delete-node/ ap-thermal-cpu2;
> >> > - /delete-node/ ap-thermal-cpu3;
> >> > - };
> >> > -};
> >> > diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
> >> > deleted file mode 100644
> >> > index 028496ebc473..000000000000
> >> > --- a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
> >> > +++ /dev/null
> >> > @@ -1,96 +0,0 @@
> >> > -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> >> > -/*
> >> > - * Copyright (C) 2023 Marvell International Ltd.
> >> > - *
> >> > - * Device tree for the CN9130-DB Com Express CPU module board.
> >> > - */
> >> > -
> >> > -#include "cn9130-db.dtsi"
> >> > -
> >> > -/ {
> >> > - model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
> >> > - compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
> >> > - "marvell,armada-ap807-quad", "marvell,armada-ap807";
> >> > -
> >> > -};
> >> > -
> >> > -&ap0_reg_sd_vccq {
> >> > - regulator-max-microvolt = <1800000>;
> >> > - states = <1800000 0x1 1800000 0x0>;
> >> > - /delete-property/ gpios;
> >> > -};
> >> > -
> >> > -&cp0_reg_usb3_vbus0 {
> >> > - /delete-property/ gpio;
> >> > -};
> >> > -
> >> > -&cp0_reg_usb3_vbus1 {
> >> > - /delete-property/ gpio;
> >> > -};
> >> > -
> >> > -&cp0_reg_sd_vcc {
> >> > - status = "disabled";
> >> > -};
> >> > -
> >> > -&cp0_reg_sd_vccq {
> >> > - status = "disabled";
> >> > -};
> >> > -
> >> > -&cp0_sdhci0 {
> >> > - status = "disabled";
> >> > -};
> >> > -
> >> > -&cp0_eth0 {
> >> > - status = "disabled";
> >> > -};
> >> > -
> >> > -&cp0_eth1 {
> >> > - status = "okay";
> >> > - phy = <&phy0>;
> >> > - phy-mode = "rgmii-id";
> >> > -};
> >> > -
> >> > -&cp0_eth2 {
> >> > - status = "disabled";
> >> > -};
> >> > -
> >> > -&cp0_mdio {
> >> > - status = "okay";
> >> > - pinctrl-0 = <&cp0_ge_mdio_pins>;
> >> > - phy0: ethernet-phy@0 {
> >> > - status = "okay";
> >> > - };
> >> > -};
> >> > -
> >> > -&cp0_syscon0 {
> >> > - cp0_pinctrl: pinctrl {
> >> > - compatible = "marvell,cp115-standalone-pinctrl";
> >> > -
> >> > - cp0_ge_mdio_pins: ge-mdio-pins {
> >> > - marvell,pins = "mpp40", "mpp41";
> >> > - marvell,function = "ge";
> >> > - };
> >> > - };
> >> > -};
> >> > -
> >> > -&cp0_sdhci0 {
> >> > - status = "disabled";
> >> > -};
> >> > -
> >> > -&cp0_spi1 {
> >> > - status = "okay";
> >> > -};
> >> > -
> >> > -&cp0_usb3_0 {
> >> > - status = "okay";
> >> > - usb-phy = <&cp0_usb3_0_phy0>;
> >> > - phy-names = "usb";
> >> > - /delete-property/ phys;
> >> > -};
> >> > -
> >> > -&cp0_usb3_1 {
> >> > - status = "okay";
> >> > - usb-phy = <&cp0_usb3_0_phy1>;
> >> > - phy-names = "usb";
> >> > - /delete-property/ phys;
> >> > -};
> >> > --
> >> > 2.51.0
> >> >
> >>
> >> --
> >> Grégory CLEMENT, Bootlin
> >> Embedded Linux and Kernel engineering
> >
> > Thanks,
> >
> > Elad.
>
> --
> Grégory CLEMENT, Bootlin
> Embedded Linux and Kernel engineering
Elad.
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