linux-kernel - Re: [PATCH 1/2] PCI: dwc: ep: Fix resizable BAR support for multi-PF configurations

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Message-ID: <5f83a07a-ef35-47e9-b40f-fc7617a4488c@ti.com>
Date: Thu, 22 Jan 2026 10:35:47 +0530
From: Aksh Garg <a-garg7@...com>
To: Niklas Cassel <cassel@...nel.org>
CC: <linux-pci@...r.kernel.org>, <jingoohan1@...il.com>, <mani@...nel.org>,
	<lpieralisi@...nel.org>, <kwilczynski@...nel.org>, <robh@...nel.org>,
	<bhelgaas@...gle.com>, <linux-kernel@...r.kernel.org>, <s-vadapalli@...com>,
	<danishanwar@...com>
Subject: Re: [PATCH 1/2] PCI: dwc: ep: Fix resizable BAR support for multi-PF
 configurations

>> -- 
>> 2.34.1
>> 
> 
> 
> Thank you for fixing this!
> 
> Reviewed-by: Niklas Cassel <cassel@...nel.org>
> 
> 
> You do need another patch in this series though, that fixes:
> https://github.com/torvalds/linux/blob/v6.19-rc6/drivers/pci/controller/dwc/pcie-designware-ep.c#L972-L986
> 
> As currently, ptm_cap_base is fetched using dw_pcie_find_ext_capability()
> instead of your new dw_pcie_ep_find_ext_capability() which takes a func_no.
> 

I examined the register spaces across different PFs to check whether all 
the PFs have the PTM capability registers, and confirmed that PTM 
capability registers exist only in PF0. PCIe r6.0 section 7.9.15 
'Precision Time Management Extended Capability (PTM Capability)' states 
that " For Endpoints and Switch Upstream Ports that support PTM, this 
Capability is required in exactly one Function of the Upstream Port and 
that Capability controls the PTM behavior of all PTM capable Functions 
associated with that Upstream Port". This indicates that PTM 
capabilities are controller-level registers rather than per-function 
registers. Hence, in my opinion, ptm_cap_base does not require 
modification, since dw_pcie_find_ext_capability() and dw_pcie_*_dbi() 
already correctly access PF0's register space, which is the expected 
behavior for controller-level PTM management.

> 
> Kind regards,
> Niklas
>