linux-kernel - Re: [EXTERNAL] Re: [PATCH 2/2] PCI: dwc: ep: Add per-PF BAR and iATU mapping support

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Message-ID: <aXDM5qpREE9FKrW6@ryzen>
Date: Wed, 21 Jan 2026 13:56:06 +0100
From: Niklas Cassel <cassel@...nel.org>
To: Aksh Garg <a-garg7@...com>
Cc: linux-pci@...r.kernel.org, jingoohan1@...il.com, mani@...nel.org,
	lpieralisi@...nel.org, kwilczynski@...nel.org, robh@...nel.org,
	bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
	s-vadapalli@...com, danishanwar@...com
Subject: Re: [EXTERNAL] Re: [PATCH 2/2] PCI: dwc: ep: Add per-PF BAR and iATU
 mapping support

On Wed, Jan 21, 2026 at 05:05:50PM +0530, Aksh Garg wrote:
> 
> 
> > On Wed, Jan 21, 2026 at 11:12:14AM +0530, Aksh Garg wrote:
> > > The commit 47a062609a30 ("PCI: designware-ep: Modify MSI and MSIX CAP
> > > way of finding") adds support for each physical function to have its
> > > own MSI and MSI-X capability structures by introducing struct
> > > dw_pcie_ep_func. However, BAR configuration and iATU mappings are still
> > > being managed globally in struct dw_pcie_ep, meaning all PFs shared the
> > > same BAR-to-iATU mapping table.
> > 
> > You are mentioning commit 47a062609a30 ("PCI: designware-ep: Modify MSI and
> > MSIX CAP way of finding"), but you should probably also mention commit
> > 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC")
> > which added support for PFs in the DWC driver.
> > 
> > That is the commit that is incorrect IMO. You cannot add support for PFs
> > and then have a different EPFs over overwriting address translation for
> > other EPFs. The design was simply broken from the start.
> > 
> 
> Yes, the commit 24ede430fa49 is indeed the culprit for this issue. Maybe the
> way I wrote this commit message confused you. I was just referring to the
> commit 47a062609a30 saying that as this commit added the feature for each PF
> to have its own MSI and MSI-X capability, I wanted to move bar_to_atu and
> epf_bar per-PF as well, such that each PF should have its own epf_bar[] and
> bar_to_atu[]. The index passed to these fields should be unique across
> PF+BAR combinations while the current implementation is only keeping it
> unique across BARs but not PFs. This results in overwriting address
> translation regions across the PFs.
> I will rephrase the commit message and add fixes tag for 24ede430fa49.
> 
> Please provide your input whether the above explaination is sufficient.
> Should I refer to commit 47a062609a30 as an example in the commit message,
> or that would not be required given the above explaination is added?

As long as you mention both commits, I think it is sufficient.


Perhaps something like:
Commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC")
added support for multiple PFs in the DWC driver.

However, this commit was incomplete, and did not properly support MSI/MSI-X
for multiple PFs, which was fixed in commit 47a062609a30 ("PCI: designware-ep:
Modify MSI and MSIX CAP way of finding").

Even with both these commits, the multiple PF support in the DWC driver is
severely broken, because one EPF for one PF will currently overwrite the address
translation done by another EPF for a completely different PF. To fix this,
just as commit 47a062609a30 ("PCI: designware-ep: Modify MSI and MSIX CAP way of
finding") did when it moved things to a per PF struct dw_pcie_ep_func, moving the
data structures needed for address translation to struct dw_pcie_ep_func.



Kind regards,
Niklas