linux-kernel - Re: [PATCH v3] arm64: errata: Workaround for SI L1 downstream coherency issue

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Message-ID: <176917501918.797415.179034767474498162.b4-ty@kernel.org>
Date: Fri, 23 Jan 2026 17:49:49 +0000
From: Will Deacon <will@...nel.org>
To: Catalin Marinas <catalin.marinas@....com>,
	Jonathan Corbet <corbet@....net>,
	Lucas Wei <lucaswei@...gle.com>
Cc: kernel-team@...roid.com,
	Will Deacon <will@...nel.org>,
	sjadavani@...gle.com,
	stable@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] arm64: errata: Workaround for SI L1 downstream coherency issue

On Wed, 14 Jan 2026 14:52:41 +0000, Lucas Wei wrote:
> When software issues a Cache Maintenance Operation (CMO) targeting a
> dirty cache line, the CPU and DSU cluster may optimize the operation by
> combining the CopyBack Write and CMO into a single combined CopyBack
> Write plus CMO transaction presented to the interconnect (MCN).
> For these combined transactions, the MCN splits the operation into two
> separate transactions, one Write and one CMO, and then propagates the
> write and optionally the CMO to the downstream memory system or external
> Point of Serialization (PoS).
> However, the MCN may return an early CompCMO response to the DSU cluster
> before the corresponding Write and CMO transactions have completed at
> the external PoS or downstream memory. As a result, stale data may be
> observed by external observers that are directly connected to the
> external PoS or downstream memory.
> 
> [...]

Applied to arm64 (for-next/errata), thanks!

[1/1] arm64: errata: Workaround for SI L1 downstream coherency issue
      https://git.kernel.org/arm64/c/3fed7e0059f0

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev