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Message-ID: <c488e092-2319-463a-b73d-68e487cf3770@oss.qualcomm.com>
Date: Mon, 26 Jan 2026 11:31:09 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>,
Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
Cc: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Odelu Kukatla <odelu.kukatla@....qualcomm.com>
Subject: Re: [PATCH 2/2] interconnect: qcom: glymur: Add Mahua SoC support
On 1/23/26 6:58 PM, Dmitry Baryshkov wrote:
> On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote:
>> Mahua is a derivative of the Glymur SoC. This patch extends the
>
> Documentation/process/submitting-patches.rst, look for 'This patch'.
>
>> Glymur driver to support Mahua by:
>>
>> 1. Adding new node definitions for interconnects that differ from Glymur
>> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
>> 2. Reusing existing Glymur definitions for identical NoCs.
>> 3. Overriding the channel and buswidth, with Mahua specific values for
>> the differing NoCs
>>
>> Co-developed-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
>> Signed-off-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
>> ---
>> drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 152 insertions(+), 1 deletion(-)
>>
>> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = {
>
> As you are patching other instances, why can't we just patch out the
> PCI_3A out of these structures?
>
>>
>> +static int glymur_qnoc_probe(struct platform_device *pdev)
>> +{
>> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
>> + llcc_mc.channels = 8;
>> + ebi.channels = 8;
>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
>> + qns_llcc.channels = 8;
>> + chm_apps.channels = 4;
>> + qnm_pcie_west.buswidth = 32;
>> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
>> + qns_pcie_west_mem_noc.buswidth = 32;
>> + }
>
> Right here, set the node entries to NULL.
+1
Konrad
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