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Message-ID: <yba2z3v7klftzhmd7bghgj4y7orun2yo2bxzlwop7xflsj7apq@nx7znegfkmhu>
Date: Tue, 27 Jan 2026 14:28:32 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
Cc: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Mike Tipton <mike.tipton@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Odelu Kukatla <odelu.kukatla@....qualcomm.com>
Subject: Re: [PATCH v2 2/2] interconnect: qcom: glymur: Add Mahua SoC support
On Tue, Jan 27, 2026 at 03:22:07AM +0000, Raviteja Laggyshetty wrote:
> Mahua is a derivative of the Glymur SoC. Extend the
> Glymur driver to support Mahua by:
>
> 1. Adding new node definitions for interconnects that differ from Glymur
> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
> 2. Reusing existing Glymur definitions for identical NoCs.
> 3. Overriding the channel and buswidth, with Mahua specific values for
> the differing NoCs
>
> Co-developed-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
> Signed-off-by: Odelu Kukatla <odelu.kukatla@....qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
> ---
> drivers/interconnect/qcom/glymur.c | 38 +++++++++++++++++++++++++++++++++-----
> 1 file changed, 33 insertions(+), 5 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
--
With best wishes
Dmitry
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