linux-kernel - Re: [PATCH v10 2/3] clk: canaan: Add clock driver for Canaan K230

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Message-ID: <6fe3250a-7ca7-418e-9f55-12597aba79ba@zohomail.com>
Date: Tue, 27 Jan 2026 21:21:11 +0800
From: Xukai Wang <kingxukai@...omail.com>
To: Jiayu Du <jiayu.riscv@...c.iscas.ac.cn>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
 Conor Dooley <conor@...nel.org>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
 Samuel Holland <samuel.holland@...ive.com>,
 Troy Mitchell <TroyMitchell988@...il.com>
Subject: Re: [PATCH v10 2/3] clk: canaan: Add clock driver for Canaan K230


On 2026/1/27 20:22, Jiayu Du wrote:
> On Tue, Jan 27, 2026 at 07:03:59PM +0800, Xukai Wang wrote:
>> On 2026/1/23 00:01, Jiayu Du wrote:
>>> On Thu, Jan 22, 2026 at 07:40:29PM +0800, Xukai Wang wrote:
>>>> On 2026/1/19 16:18, Jiayu Du wrote:
>>>>>> +
>>>>>> +K230_CLK_GATE_FORMAT(hs_hclk_src_gate,
>>>>>> +		     K230_HS_HCLK_SRC_GATE,
>>>>>> +		     0x18, 0, 0, 0,
>>>>>> +		     &hs_hclk_high_src_rate.clk.hw);
>>>>> Here, you replaced hs_hclk_high_gate(in v9) with hs_hclk_high_src_rate,
>>>> I'm a bit confused, as I don't recall making these specific changes.
>>>> Looking at the code below, the only difference between v9 and v10 is
>>>> within the K230_CLK_GATE_FORMAT(hs_hclk_src_gate, ...) definition, where
>>>> the second parameter changed from 1 to 0. Everything else appears
>>>> consistent. Could you clarify which change you were referring to?
>>>>> but after my board test, I find that when hs_hclk_high_gate is turned
>>>>> off, the mmc/sd and other high-speed subsystems can not work. So maybe
>>>>> you should not change the hs_hclk_high_gate to hs_hclk_high_src_rate.
>>>> Regarding the clock management, I recommend explicitly enabling
>>>> hs_hclk_high_gateas it will be closed by `close unused clocks`.
>>> Sorry, you are right. It was me who made the changes locally. And I
>>> saw your reply to this email[1], which you said According to the vendor's
>>> code, the parent clock of hs_hclk_src is hs_hclk_high_src.
>>>
>>> Indeed, the parent clock of hs_hclk_src is hs_hclk_high_src. 
>>> but hs_hclk_high_gate is the gate of hs_hclk_high_src. 
>> No. It seems there is some confusion. The hs_hclk_high_src does not have
>> a gate.
> In this code segment of the vendor[1], it states that hs_hclk_high is
> indeed the downstream gate of hs_hclk_high_src. Once hs_hclk_high is turned
> off, all the high-speed peripherals such as USB, MMC, and SD will fail.
> This indicates that in the hardware, the gate bit1 actually controls the
> overall clock switch of the high speed system.
>
> I understand that hs_sd0/1_ahb_gate should be enabled during the SD driver
> probe, and hs_usb0/1_ahb_gate should be enabled during the USB driver probe,
> but currently there is NO clear driver to ENABLE hi_hclk_high_gate. 
>
> So in your code, I think hs_hclk_high_gate should be the gate of 
> hs_hclk_high_src_rate. And hs_hclk_high_gate should be the parent of
> hs_hclk_src_gate.
>
> link: https://github.com/kendryte/k230_sdk/blob/main/src/little/linux/arch/riscv/boot/dts/kendryte/clock_provider.dtsi#L497 [1]

OK, I understandthe issue you described. The namespace in the vendor's
code is quite poorly structured, so I will rename hs_hclk_high_src to
hs_hclk_high and hs_hclk_src to hs_hclk, to better reflect that they are
part of the same clock. The updated clock tree is as follows:

      hs_hclk_high_gate
          hs_hclk_high_rate
             hs_hclk_gate
                hs_hclk_rate
                   hs_sd0_ahb_gate
                   hs_sd1_ahb_gate
                   hs_ssi1_ahb_gate
                   hs_ssi2_ahb_gate
                   hs_usb0_ahb_gate
                   hs_usb1_ahb_gate

This revision clarifies both the clock tree structure and namespace, and
once you enable a leaf node in the clock tree, such as hs_sd0_ahb_gate,
the top-level gate clock will be automatically enabled.

>
>> The clock tree is as follow:
>>
>>        pll0_div4
>>           hs_hclk_high_src_rate
>>              hs_hclk_high_gate
>>              hs_hclk_src_gate
>>                 hs_hclk_src_rate
>>                    hs_sd0_ahb_gate
>>                    hs_sd1_ahb_gate
>>                    hs_ssi1_ahb_gate
>>                    hs_ssi2_ahb_gate
>>                    hs_usb0_ahb_gate
>>                    hs_usb1_ahb_gate
>>
>>> So, what you mean is
>>> that you will add the CLK_IS_CRITICAL flag to the hs_hclk_high_gate?
>> No, I don't intend to add CLK_IS_CRITICAL flag. Instead, I recommend you
>> to explicitly enable the clock by using clk_prepare_enable in your driver.
> I think there is NO clear driver to ENABLE hi_hclk_high_gate.
>
> Regards,
> Jiayu Du
>
>>> Link: https://lore.kernel.org/all/159615d3-cc52-43be-bf6d-5fe717ef1cc4@zohomail.com/ [1]
>>>
>>> Regards,
>>> Jiayu Du
>>>