linux-kernel - Re: [PATCH] rust: add `CacheAligned` for easy cache line alignment of values

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Message-ID: <aXohLx77gHe9b_oJ@google.com>
Date: Wed, 28 Jan 2026 14:46:07 +0000
From: Alice Ryhl <aliceryhl@...gle.com>
To: Gary Guo <gary@...yguo.net>
Cc: Alexandre Courbot <acourbot@...dia.com>, Andreas Hindborg <a.hindborg@...nel.org>, 
	Miguel Ojeda <ojeda@...nel.org>, Boqun Feng <boqun.feng@...il.com>, 
	"Björn Roy Baron" <bjorn3_gh@...tonmail.com>, Benno Lossin <lossin@...nel.org>, 
	Trevor Gross <tmgross@...ch.edu>, Danilo Krummrich <dakr@...nel.org>, linux-kernel@...r.kernel.org, 
	rust-for-linux@...r.kernel.org
Subject: Re: [PATCH] rust: add `CacheAligned` for easy cache line alignment of values

On Wed, Jan 28, 2026 at 02:41:05PM +0000, Gary Guo wrote:
> On Wed Jan 28, 2026 at 2:25 PM GMT, Alexandre Courbot wrote:
> > On Wed Jan 28, 2026 at 11:05 PM JST, Andreas Hindborg wrote:
> > While 64 bytes is the most common cache line size, AFAIK this is not
> > a universal value? Can we expose and use `L1_CACHE_BYTES` here?
> 
> On all archs that we do support today, I think the value is always 64. However
> it'd worth putting a FIXME or TODO (or assertion, maybe?) in case new archs gets
> addded where this isn't true.

Are you sure? From Tokio:

> Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
> lines at a time, so we have to align to 128 bytes rather than 64.
>
> Sources:
> - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
> - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
>
> ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
>
> Sources:
> - https://www.mono-project.com/news/2016/09/12/arm64-icache/
>
> powerpc64 has 128-byte cache line size.
>
> Sources:
> - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9

https://github.com/tokio-rs/tokio/blob/master/tokio/src/util/cacheline.rs#L85