linux-kernel - Re: [PATCH] rust: add `CacheAligned` for easy cache line alignment of values

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Message-Id: <DG0AU8J5K0SA.2SJVFWGAI98RZ@garyguo.net>
Date: Wed, 28 Jan 2026 14:41:05 +0000
From: "Gary Guo" <gary@...yguo.net>
To: "Alexandre Courbot" <acourbot@...dia.com>, "Andreas Hindborg"
 <a.hindborg@...nel.org>
Cc: "Miguel Ojeda" <ojeda@...nel.org>, "Boqun Feng" <boqun.feng@...il.com>,
 "Gary Guo" <gary@...yguo.net>, Björn Roy Baron
 <bjorn3_gh@...tonmail.com>, "Benno Lossin" <lossin@...nel.org>, "Alice
 Ryhl" <aliceryhl@...gle.com>, "Trevor Gross" <tmgross@...ch.edu>, "Danilo
 Krummrich" <dakr@...nel.org>, <linux-kernel@...r.kernel.org>,
 <rust-for-linux@...r.kernel.org>
Subject: Re: [PATCH] rust: add `CacheAligned` for easy cache line alignment
 of values

On Wed Jan 28, 2026 at 2:25 PM GMT, Alexandre Courbot wrote:
> On Wed Jan 28, 2026 at 11:05 PM JST, Andreas Hindborg wrote:
>> `CacheAligned` allows to easily align values to a 64 byte boundary.
>>
>> An example use case is the kernel `struct spinlock`. This struct is 4 bytes
>> on x86 when lockdep is not enabled. The structure is not padded to fit a
>> cache line. The effect of this for `SpinLock` is that the lock variable and
>> the value protected by the lock might share a cache line, depending on the
>> alignment requirements of the protected value. Wrapping the value in
>> `CacheAligned` to get a `SpinLock<CacheAligned<T>>` solves this problem.
>>
>> Signed-off-by: Andreas Hindborg <a.hindborg@...sung.com>
>> ---
>> Signed-off-by: Andreas Hindborg <a.hindborg@...nel.org>
>> ---
>>  rust/kernel/cache_aligned.rs | 59 ++++++++++++++++++++++++++++++++++++++++++++
>>  rust/kernel/lib.rs           |  2 ++
>>  2 files changed, 61 insertions(+)
>>
>> diff --git a/rust/kernel/cache_aligned.rs b/rust/kernel/cache_aligned.rs
>> new file mode 100644
>> index 0000000000000..9c33b8613c077
>> --- /dev/null
>> +++ b/rust/kernel/cache_aligned.rs
>> @@ -0,0 +1,59 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +
>> +use kernel::try_pin_init;
>> +use pin_init::{
>> +    pin_data,
>> +    pin_init,
>> +    PinInit, //
>> +};
>> +
>> +/// Wrapper type that alings content to a 64 byte cache line.
>
> nit: s/alings/aligns
>
>> +#[repr(align(64))]
>
> While 64 bytes is the most common cache line size, AFAIK this is not
> a universal value? Can we expose and use `L1_CACHE_BYTES` here?

Unfortunately `repr(align())` does not accept expression or macro invocations.
It's still possible with code-generation, but it'll be more tricky.

On all archs that we do support today, I think the value is always 64. However
it'd worth putting a FIXME or TODO (or assertion, maybe?) in case new archs gets
addded where this isn't true.

Best,
Gary