linux-kernel - Re: [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT

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Message-ID: <4040610.5fSG56mABF@workhorse>
Date: Wed, 28 Jan 2026 17:31:35 +0100
From: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
To: Alexander Stein <alexander.stein@...tq-group.com>,
 Mark Brown <broonie@...nel.org>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
 Dong Aisheng <aisheng.dong@....com>,
 Matthias Brugger <matthias.bgg@...il.com>,
 Yassine Oudjana <y.oudjana@...tonmail.com>,
 Laura Nao <laura.nao@...labora.com>,
 Nícolas F. R. A. Prado <nfraprado@...labora.com>,
 Chia-I Wu <olvaffe@...il.com>, Chen-Yu Tsai <wenst@...omium.org>,
 kernel@...labora.com, linux-clk@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc

On Wednesday, 28 January 2026 16:21:47 Central European Standard Time Mark Brown wrote:
> On Wed, Jan 28, 2026 at 03:55:54PM +0100, Alexander Stein wrote:
> 
> > This is for TQMa8MPxL/MBa8MPxL:
> 
> > [    1.452788] __clk_core_init: enabling parent audio_pll1_out for clkout1_sel
> > [    1.457677] __clk_core_init: disabling parent audio_pll1_out for clkout1_sel
> > [    1.464270] __clk_core_init: enabling parent audio_pll1_out for clkout2_sel
> > [    1.471760] __clk_core_init: disabling parent audio_pll1_out for clkout2_sel
> > [    1.478360] __clk_core_init: enabling parent sys_pll2_500m for arm_a53_div
> > [    1.485259] __clk_core_init: disabling parent sys_pll2_500m for arm_a53_div
> 
> As expected same result on i.MX8MP-EVK.
> 

This one puzzles me a little. arm_a53_div is neither marked critical
nor is its parent. If arm_a53_div is required for the system to function,
then I'd have expected at least it to be marked as critical, allowing us
to do the workaround in init I proposed as an alternate solution for the
stm32mp1 in my other reply.

Also, after reading the code some more, I think that alternate solution
has a simpler implementation: move the parent disable to after the

  if (core->flags & CLK_IS_CRITICAL) {

check in __clk_core_init.

One explanation is that some other critical clock hangs off sys_pll2_500m,
but we're spoiled for choice here. I can't think of a simple fix right now
that I feel confident in.

Every IMX8MP composite clock that isn't critical seems to set
IMX_COMPOSITE_CLK_FLAGS_DEFAULT, which includes CLK_OPS_PARENT_ENABLE,
which seems like a pretty weird choice to make when you then rely on
the parent not getting touched during __clk_core_init.

I will try to get an RFC fix out tonight (CET). I think STM32MP1 is
falling over because I messed up, and i.MX8MP is falling over due to
a combination of me messing up and its clock driver messing up.

Kind regards,
Nicolas Frattaroli