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Message-ID: <aXmlCbEUsqZEDYNP@shlinux89>
Date: Wed, 28 Jan 2026 13:56:25 +0800
From: Peng Fan <peng.fan@....nxp.com>
To: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@...i.sm>
Cc: Abel Vesa <abelvesa@...nel.org>, Peng Fan <peng.fan@....com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Lucas Stach <l.stach@...gutronix.de>,
Anson Huang <anson.huang@....com>, Bai Ping <ping.bai@....com>,
linux-clk@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kernel@...i.sm
Subject: Re: [PATCH] clk: imx8mq: Correct the CSI PHY sels
On Wed, Jan 28, 2026 at 12:47:21AM +0100, Sebastian Krzyszkowiak wrote:
>According to i.MX 8M Quad Reference Manual (Section 5.1.2 Table 5-1)
>MIPI_CSI1_PHY_REF_CLK_ROOT and MIPI_CSI2_PHY_REF_CLK_ROOT have
>SYSTEM_PLL2_DIV3 available as their second source, which corresponds
>to sys2_pll_333m rather than sys2_pll_125m.
>
>Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
>Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@...i.sm>
Thanks for the fix.
Reviewed-by: Peng Fan <peng.fan@....com>
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