[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20260128073532.2904161-3-ziniu.wang_1@nxp.com>
Date: Wed, 28 Jan 2026 15:35:32 +0800
From: ziniu.wang_1@....com
To: shawnguo@...nel.org,
s.hauer@...gutronix.de,
frank.li@....com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org
Cc: kernel@...gutronix.de,
festevam@...il.com,
devicetree@...r.kernel.org,
imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 3/3] arm64: dts: imx91-11x11-evk: change usdhc tuning step for eMMC and SD
From: Luke Wang <ziniu.wang_1@....com>
For eMMC and SD, there are two tuning pass windows and the gap between
those two windows may only have one cell. If tuning step > 1, the gap may
just be skipped and host assumes those two windows as a continuous
windows. This will cause a bad delay cell near the gap to be selected.
For SDIO, the gap is big enough, default tuning step is fine.
Signed-off-by: Luke Wang <ziniu.wang_1@....com>
---
arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
index aca78768dbd4..4164d9e4e0fd 100644
--- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
@@ -415,6 +415,7 @@ &usdhc1 {
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ fsl,tuning-step = <1>;
status = "okay";
};
@@ -429,6 +430,7 @@ &usdhc2 {
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <®_usdhc2_vmmc>;
+ fsl,tuning-step = <1>;
status = "okay";
};
--
2.34.1
Powered by blists - more mailing lists