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Message-Id: <20260128073532.2904161-2-ziniu.wang_1@nxp.com>
Date: Wed, 28 Jan 2026 15:35:31 +0800
From: ziniu.wang_1@....com
To: shawnguo@...nel.org,
s.hauer@...gutronix.de,
frank.li@....com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org
Cc: kernel@...gutronix.de,
festevam@...il.com,
devicetree@...r.kernel.org,
imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 2/3] arm64: dts: imx93-11x11-evk: change usdhc tuning step for eMMC and SD
From: Luke Wang <ziniu.wang_1@....com>
For eMMC and SD, there are two tuning pass windows and the gap between
those two windows may only have one cell. If tuning step > 1, the gap may
just be skipped and host assumes those two windows as a continuous
windows. This will cause a bad delay cell near the gap to be selected.
For SDIO, the gap is big enough, default tuning step is fine.
Signed-off-by: Luke Wang <ziniu.wang_1@....com>
---
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index b94a24193e19..6da2d25acbd0 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -632,6 +632,7 @@ &usdhc1 {
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
+ fsl,tuning-step = <1>;
status = "okay";
};
@@ -644,6 +645,7 @@ &usdhc2 {
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
bus-width = <4>;
+ fsl,tuning-step = <1>;
status = "okay";
no-mmc;
};
--
2.34.1
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