linux-kernel - Re: [v5,2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon

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Message-ID: <20260129051035.375905-1-kuba@kernel.org>
Date: Wed, 28 Jan 2026 21:10:35 -0800
From: Jakub Kicinski <kuba@...nel.org>
To: dan.carpenter@...aro.org
Cc: Jakub Kicinski <kuba@...nel.org>,
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	davem@...emloft.net,
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Subject: Re: [v5,2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon

This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.

For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon

This commit adds the nxp,phy-sel property to the S32 DWMAC binding,
allowing access to the GMAC_0_CTRL_STS register via a syscon interface
instead of the previous ad-hoc direct register mapping.

> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..65633b10e49e 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml

[ ... ]

> +  nxp,phy-sel:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the GPR syscon node
> +          - description: offset of PHY selection register
> +    description:
> +      This phandle points to the GMAC_0_CTRL_STS register which controls the
> +      GMAC_0 configuration options.  The register lets you select the PHY
> +      interface and the PHY mode.  It also controls if the FTM_0 or FTM_1
> +      FlexTimer Modules connect to GMAC_O.
                                       ^^^^^^

Should this be GMAC_0 (with a zero) instead of GMAC_O (with a letter O)?
The rest of the description uses GMAC_0_CTRL_STS and GMAC_0 consistently.
-- 
pw-bot: cr