linux-kernel - Re: [PATCH v2 2/2] x86/cpu/intel: Add implicit RFDS mitigation for Goldmont and Tremont-D

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Message-ID: <1e142e20-e3b8-4bc7-9d92-c3001b11a5fb@intel.com>
Date: Fri, 30 Jan 2026 09:50:48 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Joongsun Moon-Lee <moontorise@....kr>, x86@...nel.org,
 Thomas Gleixner <tglx@...nel.org>, Ingo Molnar <mingo@...hat.com>,
 Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>
Cc: "H . Peter Anvin" <hpa@...or.com>, Peter Zijlstra <peterz@...radead.org>,
 Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
 Josh Poimboeuf <jpoimboe@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] x86/cpu/intel: Add implicit RFDS mitigation for
 Goldmont and Tremont-D

On 1/30/26 04:33, Joongsun Moon-Lee wrote:
...
> Force X86_FEATURE_RFDS_CLEAR for these models in init_intel() to enable
> the mitigation automatically. For Tremont-D, limit the quirk to stepping 7,
> as stepping 5 does not support mitigation according to Intel's guidance [1].

Thank $DEITY for the CSV:

> https://github.com/intel/Intel-affected-processor-list/blob/main/Intel_affected_processor_list.csv

$ csvtool namedcol "CPUID Family_Model,Stepping,MCU Update,Register File
Data Sampling (RFDS) (Floating Point/Integer / Single
Instruction/Multiple Data) - CVE-2023-28746 - INTEL-SA-00898"
Intel_affected_processor_list.csv \
	| egrep '^06_86H|06_5CH'

Yields:

06_5CH,A,0x28,      MCU+Software
06_86H,5,0x4c000026,No planned mitigation
06_86H,7,0x4c000026,MCU+Software

Which is actually readable, unlike the HTML table.

But, honestly, other than the table saying "MCU+Software", I don't see
any indication that VERW does what you want it to do on these CPUs.

Intel's guidance[1] only says:

	... software should only apply the VERW mitigations as an RFDS
	mitigation if RFDS_CLEAR is enumerated.

So I think you're going _entirely_ on the "MCU+Software" in the
table/csv above. Is there anything else? It sounds like you haven't
actually tested in VERW does what you want it to.

> +/*
> + * These CPUs mitigate RFDS via VERW but do not enumerate the RFDS_CLEAR bit
> + * in IA32_ARCH_CAPABILITIES MSR.
> + */
> +static const struct x86_cpu_id implicit_rfds_list[] = {
> +	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,		0),
> +	X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 7, 7,	0),
> +	{},
> +};

Please make this look like all the other lists and make an attempt to
vertically align things.

1.
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/register-file-data-sampling.html