linux-kernel - [PATCH v2 2/2] x86/cpu/intel: Add implicit RFDS mitigation for Goldmont and Tremont-D

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Message-ID: <20260130123340.1544-3-moontorise@cfg.kr>
Date: Fri, 30 Jan 2026 21:33:40 +0900
From: Joongsun Moon-Lee <moontorise@....kr>
To: x86@...nel.org,
	Thomas Gleixner <tglx@...nel.org>,
	Ingo Molnar <mingo@...hat.com>,
	Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>
Cc: "H . Peter Anvin" <hpa@...or.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
	Josh Poimboeuf <jpoimboe@...nel.org>,
	linux-kernel@...r.kernel.org,
	Joongsun Moon-Lee <moontorise@....kr>
Subject: [PATCH v2 2/2] x86/cpu/intel: Add implicit RFDS mitigation for Goldmont and Tremont-D

Goldmont and Tremont-D CPUs support RFDS mitigation via VERW but do not
enumerate the RFDS_CLEAR bit in the IA32_ARCH_CAPABILITIES MSR.

Force X86_FEATURE_RFDS_CLEAR for these models in init_intel() to enable
the mitigation automatically. For Tremont-D, limit the quirk to stepping 7,
as stepping 5 does not support mitigation according to Intel's guidance [1].

To ensure safety, only enable this quirk when X86_BUG_OLD_MICROCODE is
not set, guaranteeing the microcode implements the VERW side-effect.

Verification was performed on an Intel NUC8CCHKR (Celeron N3350 / Goldmont)
with microcode 0x48, confirming the status change from
"Vulnerable: No microcode" to "Mitigation: Clear Register File".

[1] https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html#tab-blade-1-1

Suggested-by: Dave Hansen <dave.hansen@...ux.intel.com>
Link: https://lore.kernel.org/all/20260129154342.3867-1-moontorise@cfg.kr/
Signed-off-by: Joongsun Moon-Lee <moontorise@....kr>
---
 arch/x86/kernel/cpu/intel.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 646ff33c4651..9867ca383621 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -531,6 +531,16 @@ static const struct x86_cpu_id zmm_exclusion_list[] = {
 	{},
 };
 
+/*
+ * These CPUs mitigate RFDS via VERW but do not enumerate the RFDS_CLEAR bit
+ * in IA32_ARCH_CAPABILITIES MSR.
+ */
+static const struct x86_cpu_id implicit_rfds_list[] = {
+	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,		0),
+	X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 7, 7,	0),
+	{},
+};
+
 static void init_intel(struct cpuinfo_x86 *c)
 {
 	early_init_intel(c);
@@ -612,6 +622,10 @@ static void init_intel(struct cpuinfo_x86 *c)
 	if (x86_match_cpu(zmm_exclusion_list))
 		set_cpu_cap(c, X86_FEATURE_PREFER_YMM);
 
+	if (x86_match_cpu(implicit_rfds_list) &&
+	    !boot_cpu_has_bug(X86_BUG_OLD_MICROCODE))
+		setup_force_cpu_cap(X86_FEATURE_RFDS_CLEAR);
+
 	/* Work around errata */
 	srat_detect_node(c);
 
-- 
2.52.0