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Message-ID: <20260130115850.253555-1-biju.das.jz@bp.renesas.com>
Date: Fri, 30 Jan 2026 11:58:41 +0000
From: Biju <biju.das.au@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>
Subject: [PATCH v2 0/4] Add support for Renesas RZ/G3L GBETH clocks
From: Biju Das <biju.das.jz@...renesas.com>
Add support for Renesas RZ/G3L GBETH clocks and reset signals.
v1->v2:
* Separated ethernet patches from series [1]
This patch series is depend upon [2]
[1] https://lore.kernel.org/all/20260128125850.425264-1-biju.das.jz@bp.renesas.com/
[2] https://lore.kernel.org/all/20260128113032.337231-1-biju.das.jz@bp.renesas.com/
Biju Das (4):
clk: renesas: rzg2l: Drop a check in rzg3s_cpg_pll_clk_recalc_rate()
clk: renesas: rzg2l: Add support for enabling PLLs
clk: renesas: r8a08g046: Add support for PLL6 clk
clk: renesas: r9a08g046: Add clock and reset signals for the GBETH IPs
drivers/clk/renesas/r9a08g046-cpg.c | 120 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.c | 70 +++++++++++++++-
drivers/clk/renesas/rzg2l-cpg.h | 10 +++
3 files changed, 197 insertions(+), 3 deletions(-)
--
2.43.0
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