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Message-ID: <20260130115850.253555-2-biju.das.jz@bp.renesas.com>
Date: Fri, 30 Jan 2026 11:58:42 +0000
From: Biju <biju.das.au@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>
Subject: [PATCH v2 1/4] clk: renesas: rzg2l: Drop a check in rzg3s_cpg_pll_clk_recalc_rate()
From: Biju Das <biju.das.jz@...renesas.com>
Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the function
is SoC specific.
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
v1->v2:
* No change
---
drivers/clk/renesas/rzg2l-cpg.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 16771a0101bd..ee92d07c6ff7 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1113,9 +1113,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
u32 nir, nfr, mr, pr, val, setting;
u64 rate;
- if (pll_clk->type != CLK_TYPE_G3S_PLL)
- return parent_rate;
-
setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
if (setting) {
val = readl(priv->base + setting);
--
2.43.0
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