linux-kernel - Re: [PATCH RFC 5/6] drm/mediatek: ovl: Disable AFBC on MT8188

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Message-ID: <f9900cc0bd27a77acf37a9a6f733d55fa8915a3d.camel@mediatek.com>
Date: Tue, 3 Feb 2026 02:41:03 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>, "simona@...ll.ch"
	<simona@...ll.ch>, AngeloGioacchino Del Regno
	<angelogioacchino.delregno@...labora.com>, "airlied@...il.com"
	<airlied@...il.com>, "greenjustin@...omium.org" <greenjustin@...omium.org>,
	"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>, "matthias.bgg@...il.com"
	<matthias.bgg@...il.com>, Nicolas Prado <nfraprado@...labora.com>
CC: Ariel D'Alessandro <ariel.dalessandro@...labora.com>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Jason-JH Lin (林睿祥) <Jason-JH.Lin@...iatek.com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, Daniel Stone <daniels@...labora.com>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"kernel@...labora.com" <kernel@...labora.com>
Subject: Re: [PATCH RFC 5/6] drm/mediatek: ovl: Disable AFBC on MT8188

On Tue, 2025-12-30 at 11:03 -0300, Nícolas F. R. A. Prado wrote:
> Despite MT8188's OVL being mostly the same IP as the OVL on MT8195, it
> does not support AFBC, even when the same register configurations are
> applied. Introduce a separate compatible for it with AFBC support
> disabled.
> 
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 196b874057ba..97f6694772d4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -762,6 +762,21 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
>  	.num_formats = ARRAY_SIZE(mt8173_formats),
>  };
>  
> +static const struct mtk_disp_ovl_data mt8188_ovl_driver_data = {
> +	.addr = DISP_REG_OVL_ADDR_MT8173,
> +	.gmc_bits = 10,
> +	.layer_nr = 4,
> +	.fmt_rgb565_is_0 = true,
> +	.smi_id_en = true,
> +	.supports_afbc = false,

Global variable is initialized to zero, so this could be drop.

Reviewed-by: CK Hu <ck.hu@...iatek.com>

> +	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
> +		       BIT(DRM_MODE_BLEND_COVERAGE) |
> +		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
> +	.formats = mt8195_formats,
> +	.num_formats = ARRAY_SIZE(mt8195_formats),
> +	.supports_clrfmt_ext = true,
> +};
> +
>  static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
>  	.addr = DISP_REG_OVL_ADDR_MT8173,
>  	.gmc_bits = 10,
> @@ -790,6 +805,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
>  	  .data = &mt8192_ovl_driver_data},
>  	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
>  	  .data = &mt8192_ovl_2l_driver_data},
> +	{ .compatible = "mediatek,mt8188-disp-ovl",
> +	  .data = &mt8188_ovl_driver_data},
>  	{ .compatible = "mediatek,mt8195-disp-ovl",
>  	  .data = &mt8195_ovl_driver_data},
>  	{},
>